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altera corporation section i?1 preliminary section i. cyclone fpga family data sheet this section provides designers with the data sheet specifications for cyclone devices. the chapters contain feature definitions of the internal architecture, configuration and jtag boundary-scan testing information, dc operating conditions, ac timing parameters, a reference to power consumption, and ordering info rmation for cyclone devices. this section contains the following chapters: chapter 1. introduction chapter 2. cyclone architecture chapter 3. configuration & testing chapter 4. dc & switching characteristics chapter 5. reference & ordering information revision history the table below shows the revision history for chapters 1 through 5 . chapter(s) date / version changes made 1 october 2003 v1.2 added 64-bit pci support information. september 2003 v1.1 updated lvds data rates to 640 mbps from 311 mbps. updated rsds feature information. may 2003 v1.0 added document to cyclone device handbook. 2 october 2003 v1.2 updated phase shift information. added 64-bit pci support information. september 2003 v1.1 updated lvds data rates to 640 mbps from 311 mbps. may 2003 v1.0 added document to cyclone device handbook. 3 may 2003 v1.0 added document to cyclone device handbook.
section i?2 altera corporation preliminary cyclone fpga family data sheet cyclone device handbook, volume 1 4 january 2004 v.1.3 added extended-temperature grade device information. updated table 4?2 . updated icc0 information in table 4?3 . october 2003 v.1.2 added clock tree information in table 4?19 . finalized timing information for ep1c3 and ep1c12 devices. updated timing information in tables 4?25 through 4?26 and tables 4?30 through 4?51 . updated pll specifications in table 4?52 . july 2003 v1.1 updated timing information. timing finalized for ep1c6 and ep1c20 devices. updated performance information. added ?pll timing? section. may 2003 v1.0 added document to cyclone device handbook. 5 may 2003 v1.0 added document to cyclone device handbook. chapter(s) date / version changes made
altera corporation 1?1 october 2003 preliminary 1. introduction introduction the cyclone tm field programmable gate array family is based on a 1.5-v, 0.13- m, all-layer copper sram process, with densities up to 20,060 logic elements (les) and up to 288 kbits of ram. with features like phase- locked loops (plls) for clocking and a dedicated double data rate (ddr) interface to meet ddr sdram an d fast cycle ram (fcram) memory requirements, cyclone devices are a cost-effective solution for data-path applications. cyclone devices support various i/o standards, including lvds at data rates up to 640 megabits per second (mbps), and 66- and 33-mhz, 64- and 32-bit peripheral component interconnect (pci), for interfacing with and supporting assp and asic devices. altera also offers new low-cost serial configuration devices to configure cyclone devices. the following shows the main sections in the cyclone fpga family data sheet: section page features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 logic array blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 logic elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 multitrack interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?12 embedded memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?18 global clock network & phase-locked loops. . . . . . . . . . . 2?29 i/o structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?39 power sequencing & hot socketing . . . . . . . . . . . . . . . . . . . . 2?55 ieee std. 1149.1 (jtag) boundary scan support . . . . . . . . . . 3?1 signaltap ii embedded logic analyzer . . . . . . . . . . . . . . . . . 3?5 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?1 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?8 timing model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?9 software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 device pin-outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 c51001-1.2
1?2 altera corporation preliminary october 2003 cyclone device handbook, volume 1 features the cyclone device family of fers the following features: 2,910 to 20,060 les, see table 1?1 up to 294,912 ram bits (36,864 bytes) supports configuration through low- cost serial configuration device support for lvttl, lvcmos, sstl-2, and sstl-3 i/o standards support for 66- and 33-mhz, 64- and 32-bit pci standard high-speed (640 mbps) lvds i/o support low-speed (311 mbps) lvds i/o support 311-mbps rsds i/o support up to two plls per device provide clock multiplication and phase shifting up to eight global clock lines with six clock resources available per logic array block (lab) row support for external memory, including ddr sdram (133 mhz), fcram, and single data rate (sdr) sdram support for multiple intellectual property (ip) cores, including altera ? megacore ? functions and altera megafunctions partners program (ampp sm ) megafunctions. table 1?1. cyclone device features feature ep1c3 ep1c4 ep1c6 ep1c12 ep1c20 les 2,910 4,000 5,980 12,060 20,060 m4k ram blocks (128 36bits)1317205264 total ram bits 59,904 78,336 92,160 239,616 294,912 plls 12222 maximum user i/o pins (1) 104 301 185 249 301 note to ta b l e 1 ? 1 : (1) this parameter includes global clock pins.
altera corporation 1?3 october 2003 preliminary features cyclone devices are available in quad flat pack (qfp) and space-saving fineline bga ? packages (see table 1?2 through 1?3 ). table 1?2. cyclone package options & i/o pin counts device 100-pin tqfp (1) 144-pin tqfp (1) , (2) 240-pin pqfp (1) 256-pin fineline bga 324-pin fineline bga 400-pin fineline bga ep1c3 65 104 ep1c4 249 301 ep1c6 98 185 185 ep1c12 173 185 249 ep1c20 233 301 notes to ta b l e 1 ? 2 : (1) tqfp: thin quad flat pack. pqfp: plastic quad flat pack. (2) cyclone devices support vertical mi gration within the same package (i.e ., designers can migrate between the ep1c3 device in the 144-pin tqfp package and the ep1c6 device in the same package) table 1?3. cyclone qfp & fineline bga package sizes dimension 100-pin tqfp 144-pin tqfp 240-pin pqfp 256-pin fineline bga 324-pin fineline bga 400-pin fineline bga pitch (mm) 0.5 0.5 0.5 1.0 1.0 1.0 area (mm 2 ) 256 484 1,024 289 361 441 length width (mm mm) 16 16 22 22 34.6 34.6 17 17 19 19 21 21
1?4 altera corporation preliminary october 2003 cyclone device handbook, volume 1
altera corporation 2?1 october 2003 preliminary 2. cyclone architecture functional description cyclone devices contain a two-dimensional row- and column-based architecture to implement custom logic. column and row interconnects of varying speeds provide signal interconnects between labs and embedded memory blocks. the logic array consists of labs, with 10 les in each lab. an le is a small unit of logic providing efficient implementation of user logic functions. labs are grouped into rows and columns across the device. cyclone devices range between 2,910 to 20,060 les. m4k ram blocks are true dual-port memory blocks with 4k bits of memory plus parity (4,608 bits). these blocks provide dedicated true dual-port, simple dual-port, or single -port memory up to 36-bits wide at up to 200 mhz. these blocks are grouped into columns across the device in between certain labs. cyclone device s offer between 60 to 288 kbits of embedded ram. each cyclone device i/o pin is fed by an i/o element (ioe) located at the ends of lab rows and columns around the periphery of the device. i/o pins support various single-ended and differential i/o standards, such as the 66- and 33-mhz, 64- and 32-bit pci standard and the lvds i/o standard at up to 640 mbps. each ioe contains a bidirectional i/o buffer and three registers for registering input, output, and output-enable signals. dual-purpose dq s, dq, and dm pins along with delay chains (used to phase-align ddr signals) provide interface support with external memory devices such as ddr sdram, and fcram devices at up to 133 mhz (266 mbps). cyclone devices provide a global clock network and up to two plls. the global clock network consists of ei ght global clock lines that drive throughout the entire device. the global clock network can provide clocks for all resources within the device, such as ioes, les, and memory blocks. the global clock lines can also be used for control signals. cyclone plls provide general-purpose clocking with clock multiplication and phase shifting as well as external ou tputs for high-speed differential i/o support. figure 2?1 shows a diagram of the cyclone ep1c12 device. c51002-1.2
2?2 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 2?1. cyclone ep1c12 device block diagram the number of m4k ram blocks, plls, rows, and columns vary per device. table 2?1 lists the resources available in each cyclone device. logic array pll ioes m4k blocks ep1c12 device table 2?1. cyclone device resources device m4k ram plls lab columns lab rows columns blocks ep1c3 1 13 1 24 13 ep1c4 1 17 2 26 17 ep1c6 1 20 2 32 20 ep1c12 2 52 2 48 26 ep1c20 2 64 2 64 32
altera corporation 2?3 october 2003 preliminary logic array blocks logic array blocks each lab consists of 10 les, le carry chains, lab control signals, a local interconnect, look-up table (lut) chai n, and register chain connection lines. the local interconnect transf ers signals between les in the same lab. lut chain connections transfer the output of one le's lut to the adjacent le for fast sequential lut connections within the same lab. register chain connections transfer the output of one le's register to the adjacent le's register within an lab. the quartus ? ii compiler places associated logic within an lab or adjacent labs, allowing the use of local, lut chain, and register chain connections for performance and area efficiency. figure 2?2 details the cyclone lab. figure 2?2. cyclone lab structure lab interconnects the lab local interconnect can drive les within the same lab. the lab local interconnect is driven by column and row interconnects and le outputs within the same lab. neighboring labs, plls, and m4k ram blocks from the left and right can also drive an lab's local interconnect through the direct link connection. the direct link connection feature minimizes the use of row and column interconnects, providing higher direct link interconnect from adjacent block direct link interconnect to adjacent block row interconnect column interconnect local interconnect lab direct link interconnect from adjacent block direct link interconnect to adjacent block
2?4 altera corporation preliminary october 2003 cyclone device handbook, volume 1 performance and flexibility. each le can drive 30 other les through fast local and direct link interconnects. figure 2?3 shows the direct link connection. figure 2?3. direct link connection lab control signals each lab contains dedicated logic for driving control signals to its les. the control signals include two clocks, two clock enables, two asynchronous clears, synchronous cl ear, asynchronous preset/load, synchronous load, and add/subtract control signals. this gives a maximum of 10 control signals at a ti me. although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. each lab can use two clocks and two clock enable signals. each lab's clock and clock enable signals are linked. for example, any le in a particular lab using the labclk1 signal will also use labclkena1 . if the lab uses both the rising and falling edges of a clock, it also uses both lab-wide clock signals. de-asserting the clock enable signal will turn off the lab-wide clock. each lab can use two asynchronous clear signals and an asynchronous load/preset signal. the as ynchronous load acts as a preset when the asynchronous load data input is tied high. lab direct link interconnect to right direct link interconnect from right lab, m4k memory block, pll, or ioe output direct link interconnect from left lab, m4k memory block, pll, or ioe output local interconnect direct link interconnect to left
altera corporation 2?5 october 2003 preliminary logic elements with the lab-wide addnsub control signal, a single le can implement a one-bit adder and subtractor. this saves le resources and improves performance for logic functions such as dsp correlators and signed multipliers that alternate between addition and subtraction depending on data. the lab row clocks [5..0] and lab local interconnect generate the lab- wide control signals. the multitrack tm interconnect's inherent low skew allows clock and control signal distribution in addition to data. figure 2?4 shows the lab control signal generation circuit. figure 2?4. lab-wide control signals logic elements the smallest unit of logic in the cy clone architecture, the le, is compact and provides advanced feat ures with efficient logic utilization. each le contains a four-input lut, which is a function generator that can implement any function of four variable s. in addition, each le contains a programmable register and carry chain with carry select capability. a single le also supports dynamic single bit addition or subtraction mode selectable by an lab-wide control signal. each le drives all types of interconnects: local, row, column, lut chain, register chain, and direct link interconnects. see figure 2?5 . labclkena1 labclk2 labclk1 labclkena2 asyncload or labpre syncload dedicated lab row clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect labclr1 labclr2 synclr addnsub 6
2?6 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 2?5. cyclone le each le's programmable register can be configured for d, t, jk, or sr operation. each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. global signals, general-purpose i/o pins, or any inte rnal logic can drive the register's clock and clear control signals. ei ther general-purpose i/o pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous data. the asynchronous load data input comes from the data3 input of the le. for combinator ial functions, the lut output bypasses the register and drives directly to the le outputs. each le has three outputs that drive the local, row, and column routing resources. the lut or register ou tput can drive these three outputs independently. two le outputs drive column or row and direct link routing connections and one drives local interconnect resources. this allows the lut to drive one output while the register drives another output. this feature, called register packing, improves device utilization because the device can use the register and the lut for unrelated labclk1 labclk2 labclr2 labpre/aload carry-in1 carry-in0 lab carry-in clock & clock enable select lab carry-out carry-out1 carry-out0 look-up ta b l e (lut) carry chain row, column, and direct link routing row, column, and direct link routing programmable register prn/ald clrn d q ena register bypass packed register select chip-wide reset labclkena1 labclkena2 synchronous load and clear logic lab-wide synchronous load lab-wide synchronous clear asynchronous clear/preset/ load logic data1 data2 data3 data4 lut chain routing to next le labclr1 local routing register chain output a data addnsub register feedback register chain routing from previous le
altera corporation 2?7 october 2003 preliminary logic elements functions. another special packing mo de allows the register output to feed back into the lut of the same le so that the register is packed with its own fan-out lut. this provides another mechanism for improved fitting. the le can also drive out registered and unregistered versions of the lut output. lut chain & register chain in addition to the three general rout ing outputs, the les within an lab have lut chain and register chain ou tputs. lut chain connections allow luts within the same lab to cascade together for wide input functions. register chain outputs allow registers within the same lab to cascade together. the register chain output allows an lab to use luts for a single combinatorial function and the register s to be used for an unrelated shift register implementation. these resources speed up connections between labs while saving local interconnect resources. ?multitrack interconnect? on page 2?12 for more information on lut chain and register chain connections. addnsub signal the le's dynamic adder/subtractor feature saves logic resources by using one set of les to implement both an adder and a subtractor. this feature is controlled by the lab-wide control signal addnsub . the addnsub signal sets the lab to perform either a + b or a ? b. the lut computes addition; subtraction is computed by adding the two's complement of the intended subtractor. the lab-wide signal converts to two's complement by inverting the b bits within the lab and setting carry-in = 1 to add one to the least si gnificant bit (lsb). the lsb of an adder/subtractor must be placed in the first le of the lab, where the lab-wide addnsub signal automatically sets the carry-in to 1. the quartus ii compiler automatically plac es and uses the adder/subtractor feature when using adder/subtra ctor parameterized functions. le operating modes the cyclone le can operate in one of the following modes: normal mode dynamic arithmetic mode each mode uses le resources differently. in each mode, eight available inputs to the le ? the four data inputs from the lab local interconnect, carry-in0 and carry-in1 from the previous le, the lab carry-in from the previous carry-chain lab, and the register chain connection ? are directed to different destinations to implement the desired logic function. lab-wide signals provide clock, asynchronous
2?8 altera corporation preliminary october 2003 cyclone device handbook, volume 1 clear, asynchronous preset/load, synchronous clear, synchronous load, and clock enable control for the register. these lab-wide signals are available in all le modes. the addnsub control signal is allowed in arithmetic mode. the quartus ii software, in conjunct ion with parameterized functions such as library of parameterized mo dules (lpm) function s, automatically chooses the appropriate mode for co mmon functions such as counters, adders, subtractors, and arithmetic functions. if required, the designer can also create special-purpose functions that specify which le operating mode to use for optimal performance. normal mode the normal mode is suitable fo r general logic applications and combinatorial functions. in normal mo de, four data inputs from the lab local interconnect are inputs to a four-input lut (see figure 2?6 ). the quartus ii compiler automatically selects the carry-in or the data3 signal as one of the inputs to the lut. each le can use lut chain connections to drive its combinatorial output directly to the next le in the lab. asynchronous load data for the register comes from the data3 input of the le. les in normal mode support packed registers. figure 2?6. le in normal mode note to figure 2?6 : (1) this signal is only allowed in normal mode if the le is at the end of an adder/subtractor chain. data1 4-input lut data2 data3 cin (from cout of previous le) data4 addnsub (lab wide) clock (lab wide) ena (lab wide) aclr (lab wide) aload (lab wide) ald/pre clrn d q ena a data sclear (lab wide) sload (lab wide) register chain connection lut chain connection register chain output row, column, and direct link routing row, column, and direct link routing local routing register feedback (1)
altera corporation 2?9 october 2003 preliminary logic elements dynamic arithmetic mode the dynamic arithmetic mode is idea l for implementing adders, counters, accumulators, wide parity functions, and comparators. an le in dynamic arithmetic mode uses four 2-input luts configurable as a dynamic adder/subtractor. the first two 2-input luts compute two summations based on a possible carry-in of 1 or 0; the other two luts generate carry outputs for the two chains of the carry select circuitry. as shown in figure 2?7 , the lab carry-in signal selects either the carry-in0 or carry-in1 chain. the selected chain's logic level in turn determines which parallel sum is generated as a combinatorial or registered output. for example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry-in0 or data1 + data2 + carry-in1 the other two luts use the data1 and data2 signals to generate two possible carry-out signals ? one for a carry of 1 and the other for a carry of 0. the carry-in0 signal acts as the carry select for the carry-out0 output and carry-in1 acts as the carry select for the carry-out1 output. les in arithmetic mode can drive out registered and unregistered versions of the lut output. the dynamic arithmetic mode also offers clock enable, counter enable, synchronous up/down control, sync hronous clear, synchronous load, and dynamic adder/subtractor options. the lab local interconnect data inputs generate the counter enable and synchronous up/down control signals. the synchronous clear and synchronous load options are lab- wide signals that affect all registers in the lab. the quartus ii software automatically places any registers that are not used by the counter into other labs. the addnsub lab-wide signal controls whether the le acts as an adder or subtractor.
2?10 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 2?7. le in dynamic arithmetic mode note to figure 2?7 : (1) the addnsub signal is tied to the carry input for the first le of a carry chain only. carry-select chain the carry-select chain provides a very fast carry-select function between les in dynamic arithmetic mode. the carry-select chain uses the redundant carry calculation to increase the speed of carry functions. the le is configured to calculate outputs for a possible carry-in of 0 and carry- in of 1 in parallel. the carry-in0 and carry-in1 signals from a lower- order bit feed forward into the higher-order bit via the parallel carry chain and feed into both the lut and the ne xt portion of the carry chain. carry- select chains can begin in any le within an lab. the speed advantage of the carry-select chain is in the parallel pre- computation of carry chains. si nce the lab carry-in selects the precomputed carry chain, not every le is in the critical path. only the propagation delays between lab carry-in generation (le 5 and le 10) are now part of the critical path. this fe ature allows the cyclone architecture to implement high-speed counters, adde rs, multipliers, pa rity functions, and comparators of arbitrary width. data1 lut data2 data3 addnsub (lab wide) clock (lab wide) ena (lab wide) aclr (lab wide) ald/pre clrn d q ena a data register chain connection lut lut lut carry-out1 carry-out0 lab carry-in carry-in0 carry-in1 (1) sclear (lab wide) sload (lab wide) lut chain connection register chain output row, column, and direct link routing row, column, and direct link routing local routing aload (lab wide) register feedback
altera corporation 2?11 october 2003 preliminary logic elements figure 2?8 shows the carry-select circuitr y in an lab for a 10-bit full adder. one portion of the lut generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum is routed to the output of the le. the register can be bypassed for simple adders or used for accumulator functions. another portion of the lut generates carry- out bits. an lab-wide carry-in bit selects which chain is used for the addition of given inputs. the ca rry-in signal for each chain, carry-in0 or carry-in1 , selects the carry-out to carry forward to the carry-in signal of the next-higher-order bit. th e final carry-out signal is routed to an le, where it is fed to local, row, or column interconnects. figure 2?8. carry select chain le4 le3 le2 le1 a1 b1 a2 b2 a3 b3 a4 b4 sum1 sum2 sum3 sum4 le10 le9 le8 le7 a7 b7 a8 b8 a9 b9 a10 b10 sum7 le6 a6 b6 sum6 le5 a5 b5 sum5 sum8 sum9 sum10 01 01 lab carry-in lab carry-out lut lut lut lut data1 lab carry-in data2 carry-in0 carry-in1 carry-out0 carry-out1 sum
2?12 altera corporation preliminary october 2003 cyclone device handbook, volume 1 the quartus ii compiler automatically creates carry chain logic during design processing, or the designer can create it manually during design entry. parameterized functions such as lpm functions automatically take advantage of carry chains fo r the appropriate functions. the quartus ii compiler creates carry chains longer than 10 les by linking labs together automatically. for enhanced fitting, a long carry chain runs vertically allowing fas t horizontal connections to m4k memory blocks. a carry chain can co ntinue as far as a full column. clear & preset logic control lab-wide signals control the logic for the register's clear and preset signals. the le directly supports an asynchronous clear and preset function. the register preset is achieved through the asynchronous load of a logic high. the direct asynchronous preset does not require a not- gate push-back technique. cyclone devices support simultaneous preset/ asynchronous load and clear signals. an asynchronous clear signal takes precedence if both signals are asserted simultaneously. each lab supports up to two clears and one preset signal. in addition to the clear and preset ports, cyclone devices provide a chip- wide reset pin ( dev_clrn ) that resets all registers in the device. an option set before compilation in the quartus ii software controls this pin. this chip-wide reset overrides all other control signals. multitrack interconnect in the cyclone architecture, conn ections between les, m4k memory blocks, and device i/o pins are provided by the multitrack interconnect structure with directdrive tm technology. the multitrack interconnect consists of contin uous, performance-optimized routing lines of different speeds used for inter- and intra-desig n block connectivi ty. the quartus ii compiler automatically places cr itical design paths on faster interconnects to improve design performance. directdrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. the multitrack interconnect and directdrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycl es that typically follow design changes and additions. the multitrack interconnect consists of row and column interconnects that span fixed distances. a routing structure with fixed length resources for all devices allows predictable and repeatable performance when
altera corporation 2?13 october 2003 preliminary multitrack interconnect migrating through different device densities. dedicated row interconnects route signals to and from labs, plls, and m4k memory blocks within the same row. these row resources include: direct link interconnects between labs and adjacent blocks r4 interconnects traversing four blocks to the right or left the direct link interconnect allows an lab or m4k memory block to drive into the local interconnect of it s left and right neighbors. only one side of a pll block interfaces with direct link and row interconnects. the direct link interconnect provides fast communication between adjacent labs and/or blocks without using row interconnect resources. the r4 interconnects span four labs, or two labs and one m4k ram block. these resources are used for fast row connections in a four-lab region. every lab has its own set of r4 interconnects to drive either left or right. figure 2?9 shows r4 interconnect connections from an lab. r4 interconnects can drive and be driven by m4k memory blocks, plls, and row ioes. for lab interfacing, a prim ary lab or lab neighbor can drive a given r4 interconnect. for r4 interconnects that drive to the right, the primary lab and right neighbor can dr ive on to the interconnect. for r4 interconnects that drive to the left, the primary lab and its left neighbor can drive on to the interconnect. r4 interconnects can drive other r4 interconnects to extend the range of labs they can drive. r4 interconnects can also drive c4 inte rconnects for connections from one row to another.
2?14 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 2?9. r4 interconnect connections notes to figure 2?9 : (1) c4 interconnects can drive r4 interconnects. (2) this pattern is repeated for every lab in the lab row. the column interconnect operates simi larly to the row interconnect. each column of labs is served by a dedicated column interconnect, which vertically routes signals to and from labs, m4k memory blocks, and row and column ioes. these column resources include: lut chain interconnects within an lab register chain interconnects within an lab c4 interconnects traversing a distance of four blocks in an up and down direction cyclone devices include an enhanced interconnect structure within labs for routing le output to le inpu t connections faster using lut chain connections and register chain conne ctions. the lut chain connection allows the combinatorial output of an le to directly drive the fast input of the le right below it, bypassing the local interconnect. these resources can be used as a high-spe ed connection for wide fan-in functions from le 1 to le 10 in the same lab. the register chain connection allows the register output of one le to connect directly to the register input of the next le in the lab for fast shift registers. the quartus ii compiler automatically takes advantage of these resources to improve utilization and performance. figure 2?10 shows the lut chain and register chain interconnects. primary lab (2) r4 interconnect driving left adjacent lab can drive onto another lab's r4 interconnect c4 column interconnects (1) r4 interconnect driving right lab neighbor lab neighbor
altera corporation 2?15 october 2003 preliminary multitrack interconnect figure 2?10. lut chain & register chain interconnects the c4 interconnects span four labs or m4k blocks up or down from a source lab. every lab has its own set of c4 interconnects to drive either up or down. figure 2?11 shows the c4 interconnect connections from an lab in a column. the c4 interconnects can drive and be driven by all types of architecture blocks, including plls, m4k memory blocks, and column and row ioes. for lab interconnection, a primary lab or its lab neighbor can drive a given c4 interconnect. c4 interconnects can drive each other to extend their rang e as well as drive row interconnects for column-to-column connections. le 1 le 2 le 3 le 4 le 5 le 6 le 7 le 8 le 9 le 10 lut chain routing to adjacent le local interconnect register chain routing to adjacen t le's register input local interconnect routing among les in the lab
2?16 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 2?11. c4 interconnect connections note (1) note to figure 2?11 : (1) each c4 interconnect can drive either up or down four rows. c4 interconnect drives local and r 4 interconnects up to four rows adjacent lab can drive onto neighboring lab's c4 interconnect c4 interconnect driving up c4 interconnect driving down lab row interconnect local interconnect
altera corporation 2?17 october 2003 preliminary multitrack interconnect all embedded blocks communicate with the logic array similar to lab- to-lab interfaces. each block (i.e., m4k memory or pll) connects to row and column interconnects and has loca l interconnect regions driven by row and column interconnects. these blocks also have direct link interconnects for fast connections to and from a neighboring lab. table 2?2 shows the cyclone device's routing scheme. table 2?2. cyclone device routing scheme source destination lut chain register chain local interconnect direct link interconnect r4 interconnect c4 interconnect le m4k ram block pll column ioe row ioe lut chain v register chain v local interconnect vvvvv direct link interconnect v r4 interconnect vvv c4 interconnect vvv le vvvvvv m4k ram block vvvv pll vvv column ioe v row ioe vvv
2?18 altera corporation preliminary october 2003 cyclone device handbook, volume 1 embedded memory the cyclone embedded memory consists of columns of m4k memory blocks. ep1c3 and ep1c6 devices have one column of m4k blocks, while ep1c12 and ep1c20 device s have two columns (see table 1?1 on page 1?2 for total ram bits per density). each m4k block can implement various types of memory with or with out parity, including true dual-port, simple dual-port, and single-port ram, rom, and fifo buffers. the m4k blocks support th e following features: 4,608 ram bits 200 mhz performance true dual-port memory simple dual-port memory single-port memory byte enable parity bits shift register fifo buffer rom mixed clock mode memory modes the m4k memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system performance. m4k blocks offer a tr ue dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. figure 2?12 shows true dual-port memory. figure 2?12. true dual-port memory configuration in addition to true dual-port memory, the m4k memory blocks support simple dual-port and single-port ram. simple dual-port memory supports a simultaneous read and wr ite. single-port memory supports non-simultaneous reads and writes. figure 2?13 shows these different m4k ram memory port configurations. data a [ ] address a [ ] wren a clock a clocken a q a [ ] aclr a data b [ ] address b [ ] wren b clock b clocken b q b [ ] aclr b ab
altera corporation 2?19 october 2003 preliminary embedded memory figure 2?13. simple dual-port & single-port memory configurations note to figure 2?13 : (1) two single-port memory blocks can be implemented in a single m4k block as long as each of the two independent block sizes is equal to or less than half of the m4k block size. the memory blocks also enable mixed-width data ports for reading and writing to the ram ports in dual-por t ram configuration. for example, the memory block can be written in 1 mode at port a and read out in 16 mode from port b. the cyclone memory architecture can implement fully synchronous ram by registering both the input and output signals to the m4k ram block. all m4k memory block inputs are registered, providing synchronous write cycles. in synchr onous operation, the memory block generates its own self-timed strobe write enable ( wren ) signal derived from a global clock. in contrast, a circuit using asynchronous ram must generate the ram wren signal while ensuring its data and address signals meet setup and hold time specifications relative to the wren signal. the output registers can be bypassed. pseudo-asynchronous reading is possible in the simple dual-port mode of m4k blocks by clocking the read enable and read address registers on the negative clock edge and bypassing the output registers. data[ ] wraddress[ ] wren inclock inclocken inaclr rdaddress[ ] rden q[ ] outclock outclocken outaclr data[ ] address[ ] wren inclock inclocken inaclr q[ ] outclock outclocken outaclr single-port memory (1) simple dual-port memory
2?20 altera corporation preliminary october 2003 cyclone device handbook, volume 1 when configured as ram or rom, th e designer can use an initialization file to pre-load the memory contents. two single-port memory blocks can be implemented in a single m4k block as long as each of the two independent block sizes is equal to or less than half of the m4k block size. the quartus ii software automatically implements larger memory by combining multiple m4k memory blocks. for example, two 256 16-bit ram blocks can be combined to form a 256 32-bit ram block. memory performance does not degrade for memory blocks using the maximum number of words allowed. logical memory blocks using less than the maximum number of words use physical blocks in parallel, eliminating any external control logic that would increase delays. to create a larger high-speed memory block, the quartus ii software automatically combines memory blocks with le control logic. parity bit support the m4k blocks support a parity bit fo r each byte. the parity bit, along with internal le logic, can implemen t parity checking for error detection to ensure data integrity. designers can also use parity-size data words to store user-specified control bits. byte enables are also available for data input masking during write operations. shift register support the designer can configure m4k memory blocks to implement shift registers for dsp applications such as pseudo-random number generators, multi-channel filterin g, auto-correlation, and cross- correlation functions. these and other dsp applications require local data storage, traditionally implemented wi th standard flip-flops, which can quickly consume many logic cells and routing resources for large shift registers. a more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementa tion with the dedicated circuitry. the size of a w m n shift register is determined by the input data width ( w ), the length of the taps ( m ), and the number of taps ( n ). the size of a w m n shift register must be less than or equal to the maximum number of memory bits in the m4k block (4,6 08 bits). the total number of shift register outputs (number of taps n width w ) must be less than the maximum data width of the m4k ram block ( 36). to create larger shift registers, multiple memory blocks are cascaded together.
altera corporation 2?21 october 2003 preliminary embedded memory data is written into each address loca tion at the falling edge of the clock and read from the address at the rising edge of the clock. the shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. figure 2?14 shows the m4k memory block in the shift register mode. figure 2?14. shift register memory configuration memory configuration sizes the memory address depths and outp ut widths can be configured as 4,096 1, 2,048 2, 1,024 4, 512 8 (or 512 9 bits), 256 16 (or 256 18 bits), and 128 32 (or 128 36 bits). the 128 32- or 36-bit configuration m -bit shift register w w m -bit shift register m -bit shift register m -bit shift register w w w w w w w m n shift register n numbe r of taps
2?22 altera corporation preliminary october 2003 cyclone device handbook, volume 1 is not available in the true dual-port mode. mixed-width configurations are also possible, allowing di fferent read and write widths. tables 2?3 and 2?4 summarize the possible m4k ram block configurations. when the m4k ram block is configured as a shift register block, the designer can create a shift register up to 4,608 bits ( w m n ). table 2?3. m4k ram block configurations (simple dual-port) read port write port 4k 12k 21k 4 512 8256 16 128 32 512 9256 18 128 36 4k 1 vvv v v v 2k 2 vvv v v v 1k 4 vvv v v v 512 8 vvv v v v 256 16 vvv v v v 128 32 vvv v v v 512 9 vv v 256 18 vv v 128 36 vv v table 2?4. m4k ram block configurations (true dual-port) port a port b 4k 12k 21k 4512 8 256 16 512 9256 18 4k 1 vvvvv 2k 2 vvvvv 1k 4 vvvvv 512 8 vvvvv 256 16 vvvvv 512 9 vv 256 18 vv
altera corporation 2?23 october 2003 preliminary embedded memory byte enables m4k blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. the byte enable s allow the input data to be masked so the device can write to specific bytes. the unwritten bytes retain the previous written value. table 2?5 summarizes the byte selection. control signals & m4k interface the m4k blocks allow for different cl ocks on their inpu ts and outputs. either of the two clocks feeding th e block can clock m4k block registers ( renwe , address, byte enable, datain , and output registers). only the output register can be bypassed. the six labclk signals or local interconnects can drive the control signals for the a and b ports of the m4k block. les can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr_b , clocken_a , and clocken_b signals, as shown in figure 2?15 . the r4, c4, and direct link interconnects from adjacent labs drive the m4k block local interconnect. the m4k blocks can communicate with labs on either the left or right side through these row resources or with lab columns on either the right or left with the column resources. up to 10 direct link input connections to the m4k block are possible from the left adjacent labs and another 10 possible from the right adjacent lab. m4k block outputs can also connect to left and right labs through 10 direct link interconnects each. figure 2?16 shows the m4k block to logic array interface. table 2?5. byte enable for m4k blocks notes (1) , (2) byteena[3..0] datain 18 datain 36 [0] = 1 [8..0] [8..0] [1] = 1 [17..9] [17..9] [2] = 1 ? [26..18] [3] = 1 ? [35..27] notes to ta b l e 2 ? 5 : (1) any combination of byte enables is possible. (2) byte enables can be used in the same manner with 8-bit words, i.e., in 16 and 32 modes.
2?24 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 2?15. m4k ram block control signals figure 2?16. m4k ram block lab row interface clocken_a renwe_a clock_a alcr_a alcr_b renwe_b dedicated lab row clocks local interconnect local interconnect local interconnect local interconnect local interconnect clocken_b clock_b 6 local interconnect local interconnect local interconnect local interconnect local interconnect dataout m4k ram block datain address 10 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab m4k ram block local interconnect region c4 interconnects r4 interconnects lab row clocks clocks byte enable control signals 6
altera corporation 2?25 october 2003 preliminary embedded memory independent clock mode the m4k memory blocks implement independent clock mode for true dual-port memory. in this mode, a separa te clock is available for each port (ports a and b). clock a controls all registers on the port a side, while clock b controls all registers on the port b side. each port, a and b, also supports independent clock enables and asynchronous clear signals for port a and b registers. figure 2?17 shows an m4k memory block in independent clock mode. figure 2?17. independent clock mode note (1) note to figure 2?17 : (1) all registers shown have asynchronous clear ports. input/output clock mode input/output clock mode can be implemented for both the true and simple dual-port memory modes. on ea ch of the two ports, a or b, one clock controls all registers for inputs into the memory block: data input, wren , and address. the other clock controls the block's data output registers. each memory block port, a or b, also supports independent clock enables and asynchronous clear signals for input and output registers. figures 2?18 and 2?19 show the memory bl ock in input/output clock mode. 6 d ena q d ena q d ena q data a [ ] address a [ ] memory block 256 16 (2) 512 8 1,024 4 2,048 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out clken a clock a d ena q wren a 6 lab row clocks q a [ ] 6 data b [ ] address b [ ] clken b clock b wren b q b [ ] ena ab ena d q d ena q byteena a [ ] byte enable a byte enable b byteena b [ ] ena d q ena d q ena d q d q write pulse generator write pulse generator
2?26 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 2?18. input/output clock mode in true dual-port mode note (1) note to figure 2?18 : (1) all registers shown have asynchronous clear ports. 6 d ena q d ena q d ena q data a [ ] address a [ ] memory block 256 16 (2) 512 8 1,024 4 2,048 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out clken a clock a d ena q wren a 6 lab row clocks q a [ ] 6 data b [ ] address b [ ] clken b clock b wren b q b [ ] ena ab ena d q ena d q ena d q d q d ena q byteena a [ ] byte enable a byte enable b byteena b [ ] ena d q write pulse generator write pulse generator
altera corporation 2?27 october 2003 preliminary embedded memory figure 2?19. input/output clock mode in simple dual-port mode note (1) note to figure 2?19 : (1) all registers shown except the rden register have asynchronous clear ports. read/write clock mode the m4k memory blocks implement re ad/write clock mode for simple dual-port memory. the designer can use up to two clocks in this mode. the write clock controls the block's data inputs, wraddress , and wren . the read clock controls the data output, rdaddress , and rden . the memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. figure 2?20 shows a memory block in read/write clock mode. 6 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] address[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out outclken inclken inclock outclock wren rden 6 lab row clocks to multitrack interconnect d ena q byteena[ ] byte enable write pulse generator
2?28 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 2?20. read/write clock mode in simple dual-port mode note (1) note to figure 2?20 : (1) all registers shown except the rden register have asynchronous clear ports. single-port mode the m4k memory blocks also support single-port mode, used when simultaneous reads and writes are not required. see figure 2?21 . a single m4k memory block can support up to two single-port mode ram blocks if each ram block is less than or equal to 2k bits in size. 6 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] address[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out rdclken wrclken wrclock rdclock wren rden 6 lab row clocks to multitrack interconnect d ena q byteena[ ] byte enable write pulse generator
altera corporation 2?29 october 2003 preliminary global clock network & phase-locked loops figure 2?21. single-port mode global clock network & phase-locked loops cyclone devices provide a global clock network and up to two plls for a complete clock management solution. global clock network there are four dedicated clock pins ( clk[3..0] , two pins on the left side and two pins on the right side) that drive the global clock network, as shown in figure 2?22 . pll outputs, logic array, and dual-purpose clock ( dpclk[7..0] ) pins can also drive the global clock network. the eight global clock lines in the global clock network drive throughout the entire device. the global clock network can provide clocks for all resources within the device ? ioes, les, and memory blocks. the global clock lines can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin, or dqs signals for ddr sdram or fcram in terfaces. internal logic can also drive the global clock network for internally generated global clocks and 6 d ena q d ena q d ena q d ena q data[ ] address[ ] ram/rom 256 16 512 8 1,024 4 2,048 2 4,096 1 data in address write enable data out outclken inclken inclock outclock write pulse generator wren 6 lab row clocks to multitrack interconnect
2?30 altera corporation preliminary october 2003 cyclone device handbook, volume 1 asynchronous clears, clock enables, or other control signals with large fanout. figure 2?22 shows the various sources that drive the global clock network. figure 2?22. global clock generation note (1) notes to figure 2?22 : (1) the ep1c3 device in the 100-pin tqfp package has five dpclk pins ( dpclk2 , dpclk3 , dpclk4 , dpclk6 , and dpclk7 ). (2) ep1c3 devices only contain one pll (pll 1). (3) the ep1c3 device in the 100-pin tqfp package does not have dedicated clock pins clk1 and clk3 . dual-purpose clock pins each cyclone device except the ep 1c3 device has eight dual-purpose clock pins, dpclk[7..0] (two on each i/o bank). ep1c3 devices have five dpclk pins in the 100-pin tqfp pack age. these dual-purpose pins 8 global clock network pll1 pll2 (2) clk0 clk1 (3) clk2 clk3 (3) dpclk1 dpclk0 dpclk4 dpclk5 dpclk2 dpclk3 dpclk7 dpclk6 2 2 from logic array from logic array 4 44 4 cyclone device
altera corporation 2?31 october 2003 preliminary global clock network & phase-locked loops can connect to the global clock network (see figure 2?22 ) for high-fanout control signals such as clocks, asynchronous clears, presets, and clock enables, or protocol control signals such as trdy and irdy for pci, or dqs signals for externa l memory interfaces. combined resources each cyclone device contains eight distinct dedicated clocking resources. the device uses multiplexers with these clocks to form six-bit buses to drive lab row clocks, column ioe clocks, or row ioe clocks. see figure 2?23 . another multiplexer at the lab level selects two of the six lab row clocks to feed the le registers within the lab. figure 2?23. global clock network multiplexers ioe clocks have row and column block regions. six of the eight global clock resources feed to these row and column regions. figure 2?24 shows the i/o clock regions. clock [7..0] column i/o region io_clk]5..0] lab row clock [5..0] row i/o region io_clk[5..0] global clocks [3..0] pll outputs [3..0] dual-purpose clocks [7..0] global clock network core logic [7..0]
2?32 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 2?24. i/o clock regions plls cyclone plls provide general-purpose clocking with clock multiplication and phase shifting as well as outputs for differential i/o support. cyclone devices contain two plls, except for the ep1c3 device, which contains one pll. column i/o clock region io_clk[5..0] column i/o clock region io_clk[5..0] 6 6 i/o clock regions i/o clock regions 8 global clock network row i/o regions cyclone logic array 6 6 lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] 6 6 6 6
altera corporation 2?33 october 2003 preliminary global clock network & phase-locked loops table 2?6 shows the pll features in cyclone devices. figure 2?25 shows a cyclone pll. figure 2?25. cyclone pll note (1) notes to figure 2?25 : (1) the ep1c3 device in the 100-pin tqfp package does not support external outputs or lvds inputs. the ep1c6 device in the 144-pin tqfp package does not support external output from pll2. (2) lvds input is supported via the secondary functi on of the dedicated clock pins. for pll 1, the clk0 pin?s secondary function is lvdsclk1p and the clk1 pin?s secondary function is lvdsclk1n . for pll 2, the clk2 pin?s secondary function is lvdsclk2p and the clk3 pin?s secondary function is lvdsclk2n . (3) pfd: phase frequency detector. table 2?6. cyclone pll features feature pll support clock multiplication and division m /( n post-scale counter) (1) phase shift down to 125-ps increments (2) , (3) programmable duty cycle yes number of internal clock outputs 2 number of external clock outputs o ne differential or one single-ended (4) notes to ta b l e 2 ? 6 : (1) the m counter ranges from 2 to 32. the n counter and the post-scale counters range from 1 to 32. (2) the smallest phase shift is determined by the voltage-controll ed oscillator (vco) period divided by 8. (3) for degree increments, cyclone device s can shift all output frequencies in increments of 45. smaller degree incr ements are possible depending on the frequency and divide parameters. (4) the ep1c3 device in the 100-pin tqfp package does not support external clock output. the ep1c6 device in the 144-pin tqfp package does no t support external clock output from pll2. charge pump vco pfd (3) loop filter clk0 or lvdsclk1p (2) clk1 or lvdsclk1n (2) n m ? t ? t global clock global clock i/o buffer g0 g1 e vco phase selection selectable at each pll output port post-scale counters
2?34 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 2?26 shows the pll global clock connections. figure 2?26. cyclone pll global clock connections notes to figure 2?26 : (1) pll 1 supports one single-ended or lvds input via pins clk0 and clk1 . (2) pll2 supports one single-ended or lvds input via pins clk2 and clk3 . (3) pll1_out and pll2_out support single-ended or lvds output. if exte rnal output is not required, these pins are available as regular user i/o pins. (4) the ep1c3 device in the 100-pin tqfp package does no t support external clock output. the ep1c6 device in the 144-pin tqfp package does not suppor t external clock output from pll2. table 2?7 shows the global clock network sources available in cyclone devices. clk0 clk1 (1) pll1 pll2 g0 g1 e g0 g1 e pll1_out (3), (4) clk2 clk3 (2) pll2_out (3), (4 ) g0 g2 g1 g3 g4 g6 g5 g7 table 2?7. global clock network sources (part 1 of 2) source gclk0 gclk1 gclk2 gclk3 gclk4 gclk5 gclk6 gclk7 pll counter output pll1 g0 vv pll1 g1 vv pll2 g0 (1) vv pll2 g1 (1) vv dedicated clock input pins clk0 vv clk1 (2) vv clk2 vv clk3 (2) vv
altera corporation 2?35 october 2003 preliminary global clock network & phase-locked loops clock multiplication & division cyclone plls provide clock synthesis for pll output ports using m /( n post scale counter) scaling factors. the input clock is divided by a pre-scale divider, n , and is then multiplied by the m feedback factor. the control loop drives the vco to match f in ( m / n ). each output port has a unique post-scale counter to divide down the high-frequency vco. for multiple pll outputs with different frequencies, the vco is set to the least-common multiple of the output frequencies that meets its frequency specifications. then, the post-scale dividers scale down the output frequency for each output port. for example, if the output frequencies required from one pll are 33 and 66 mhz, the vco is set to 330 mhz (the least-common multiple in the vco's range). each pll has one pre-scale divider, n , that can range in value from 1 to 32. each pll also has one multiply divider, m , that can range in value from 2 to 32. global clock outputs have two post scal e g dividers for global clock outputs, and external cl ock outputs have an e divider for external clock output, both ranging fr om 1 to 32. the quartus ii software automatically chooses the appropriat e scaling factors according to the input frequency, multiplication, and division values entered. dual-purpose clock pins dpclk0 (3) v dpclk1 (3) v dpclk2 v dpclk3 v dpclk4 v dpclk5 (3) v dpclk6 v dpclk7 v notes to ta b l e 2 ? 7 : (1) ep1c3 devices only have one pll (pll 1). (2) ep1c3 devices in the 100-pin tqfp package do not have dedicated clock pins clk1 and clk3 . (3) ep1c3 devices in the 100-pin tqfp package do not have the dpclk0 , dpclk1 , or dpclk5 pins. table 2?7. global clock network sources (part 2 of 2) source gclk0 gclk1 gclk2 gclk3 gclk4 gclk5 gclk6 gclk7
2?36 altera corporation preliminary october 2003 cyclone device handbook, volume 1 external clock inputs each pll supports single-ended or differential inputs for source- synchronous receivers or for general-purpose use. the dedicated clock pins ( clk[3..0] ) feed the pll inputs. these dual-purpose pins can also act as lvds input pins. see figure 2?25 . table 2?8 shows the i/o standards supported by pll input and output pins. for more information on lvds i/o support, see ?lvds i/o pins? on page 2?54 . external clock outputs each pll supports one differential or one single-ended output for source- synchronous transmitters or for gene ral-purpose external clocks. if the pll does not use these pll_out pins, the pins are available for use as general-purpose i/o pins. the pll_out pins support all i/o standards shown in table 2?8 . the external clock outputs do not have their own v cc and ground voltage supplies. therefore, to minimize jitter, do not place switching i/o pins next to these output pins. the ep1c3 device in the 100-pin tqfp package table 2?8. pll i/o standards i/o standard clk input extclk output 3.3-v lvttl/lvcmos vv 2.5-v lvttl/lvcmos vv 1.8-v lvttl/lvcmos vv 1.5-v lvcmos vv 3.3-v pci vv lv d s vv sstl-2 class i vv sstl-2 class ii vv sstl-3 class i vv sstl-3 class ii vv differential sstl-2 v
altera corporation 2?37 october 2003 preliminary global clock network & phase-locked loops does not have dedicated clock output pins. the ep1c6 device in the 144-pin tqfp package only support s dedicated clock outputs from pll 1. clock feedback cyclone plls have three modes for multiplication and/or phase shifting: zero delay buffer mode ? the external clock output pin is phase- aligned with the clock input pin for zero delay. normal mode ? if the design uses an internal pll clock output, the normal mode compensates for the in ternal clock delay from the input clock pin to the ioe registers. the external clock output pin is phase shifted with respect to the clock input pin if connected in this mode. the designer defines which internal clock output from the pll should be phase-aligned to compensate for internal clock delay. no compensation mode ? in this mode, the pll will not compensate for any clock networks. phase shifting cyclone plls have an advanced clock shift capability that enables programmable phase shifts. designers can enter a phase shift (in degrees or time units) for each pll clock output port or for all outputs together in one shift. designers can perform phase shifting in time units with a resolution range of 125 to 250 ps. the finest resolution equals one eighth of the vco period. the vco period is a function of the frequency input and the multiplication and division factors. each clock output counter can choose a different phase of the vco period from up to eight taps. designers can use this clock output co unter along with an initial setting on the post-scale counter to achiev e a phase-shift range for the entire period of the output clock. the phase tap feedback to the m counter can shift all outputs to a single phase. the quartus ii software automatically sets the phase taps and counter se ttings according to the phase shift entered. lock detect signal the lock output indicates that there is a stable clock output signal in phase with the reference clock. withou t any additional circuitry, the lock signal may toggle as the pll begins tracking the reference clock. therefore, the designer may need to gate the lock signal for use as a system-control signal. for correct operation of the lock circuit below ?20 c, f in/n > 200 mhz.
2?38 altera corporation preliminary october 2003 cyclone device handbook, volume 1 programmable duty cycle the programmable duty cycle allows plls to generate clock outputs with a variable duty cycle. this feature is supported on each pll post-scale counter (g0, g1, e). the duty cycle setting is achieved by a low- and high- time count setting for the post-scale dividers. the quartus ii software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. control signals there are three control signals for clearing and enabling plls and their outputs. the designer can use these signals to control pll resynchronization and the ability to gate pll output clocks for low- power applications. the pllenable signal enables and disables plls. when the pllenable signal is low, the clock output ports are driven by ground and all the plls go out of lock. when the pllenable signal goes high again, the plls relock and resynchronize to the input clocks. an input pin or le output can drive the pllenable signal. the areset signals are reset/resynchronization inputs for each pll. cyclone devices can drive these input signals from input pins or from les. when areset is driven high, the pll counters will reset, clearing the pll output and placing the pll ou t of lock. when driven low again, the pll will resynchronize to its input as it relocks. the pfdena signals control the phase frequency detector (pfd) output with a programmable gate. if you di sable the pfd, the vco will operate at its last set value of control voltage and frequency with some drift, and the system will continue running when the pll goes out of lock or the input clock disables. by maintaining the last locked frequency, the system has time to store its current settings before shutting down. the designer can either use their own control signal or gated locked status signals to trigger the pfdena signal. f for more information on cyclone plls, see chapter 6, using plls in cyclone devices .
altera corporation 2?39 october 2003 preliminary i/o structure i/o structure ioes support many features, including: differential and single-ended i/o standards 3.3-v, 64- and 32-bit, 66- and 33-mhz pci compliance joint test action group (jtag) boundary-scan test (bst) support output drive strength control weak pull-up resistors during configuration slew-rate control tri-state buffers bus-hold circuitry programmable pull-up resistors in user mode programmable input and output delays open-drain outputs dq and dqs i/o pins cyclone device ioes contain a bidirectional i/o buffer and three registers for complete embedded bidirectional single data rate transfer. figure 2?27 shows the cyclone ioe structure. the ioe contains one input register, one output register, and one output enable register. the designer can use the input registers for fast setup times and output registers for fast clock-to-output times. additionally, the designer can use the output enable (oe) register for fast clock-to-output enable timing. the quartus ii software automatically duplicates a single oe register that controls multiple output or bidirectional pins. ioes can be used as input, output, or bidirectional pins.
2?40 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 2?27. cyclone ioe structure note to figure 2?27 : (1) there are two paths available for combinatorial inputs to the logic array. each path contains a unique programmable delay chain. the ioes are located in i/o blocks around the periphery of the cyclone device. there are up to three ioes per row i/o block and up to three ioes per column i/o block (column i/o bl ocks span two columns). the row i/o blocks drive row, column, or direct link interconnects. the column i/o blocks drive column interconnects. figure 2?28 shows how a row i/o block connects to the logic array. figure 2?29 shows how a column i/o block connects to the logic array. output register output combinatorial input (1) input oe register oe input register logic array dq dq dq
altera corporation 2?41 october 2003 preliminary i/o structure figure 2?28. row i/o block connection to the interconnect notes to figure 2?28 : (1) the 21 data and control signals consist of three data out lines, io_dataout[2..0] , three output enables, io_coe[2..0] , three input clock enables, io_cce_in[2..0] , three output clock enables, io_cce_out[2..0] , three clocks, io_cclk[2..0] , three asynchronous clear signals, io_caclr[2..0] , and three synchronous clear signals, io_csclr[2..0] . (2) each of the three ioes in the row i/o block can have one io_datain input (combinatorial or registered) and one comb_io_datain (combinatorial) input. 21 r4 interconnects c4 interconnects i/o block local interconnect 21 data and control signals from logic array (1) io_datain[2..0] and comb_io_datain[2..0] (2) io_clk[5:0] row i/o block contains up to three ioes direct link interconnect to adjacent lab direct link interconnect from adjacent lab lab local interconnect lab row i/o block
2?42 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 2?29. column i/o block connection to the interconnect notes to figure 2?29 : (1) the 21 data and control signals consist of three data out lines, io_dataout[2..0] , three output enables, io_coe[2..0] , three input clock enables, io_cce_in[2..0] , three output clock enables, io_cce_out[2..0] , three clocks, io_cclk[2..0] , three asynchronous clear signals, io_caclr[2..0] , and three synchronous clear signals, io_csclr[2..0] . (2) each of the three ioes in the column i/o block can have one io_datain input (combinatorial or registered) and one comb_io_datain (combinatorial) input. 21 data & control signals from logic array (1) column i/o block contains up to three ioes i/o block local interconnect io_datain[2:0] & comb_io_datain[2..0] (2) r4 interconnects lab local interconnect c4 interconnects 21 lab lab lab io_clk[5..0] column i/o block
altera corporation 2?43 october 2003 preliminary i/o structure the pin's datain signals can drive the logic array. the logic array drives the control and data signals, providing a flexible routing resource. the row or column ioe clocks, io_clk[5..0] , provide a dedicated routing resource for low-skew, high-speed clocks. the global clock network generates the ioe clocks that feed the row or column i/o regions (see ?global clock network & phase-locked loops? on page 2?29 ). figure 2?30 illustrates the signal paths through the i/o block. figure 2?30. signal path through the i/o block each ioe contains its own control signal selection for the following control signals: oe , ce_in , ce_out , aclr / preset , sclr / preset , clk_in , and clk_out . figure 2?31 illustrates the control signal selection. row or column io_clk[5..0] io_datain comb_io_datain io_dataout io_coe oe ce_in ce_out io_cce_in aclr/preset io_cce_out sclr io_caclr clk_in io_cclk clk_out dataout data and control signal selection ioe to logic array from logic array to other ioes io_csclr
2?44 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 2?31. control signal selection per ioe in normal bidirectional operation, th e designer can use the input register for input data requiring fast setup time s. the input register can have its own clock input and clock enable separate from the oe and output registers. the output register can be used for data requiring fast clock-to- output performance. the oe register is available for fast clock-to-output enable timing. the oe and output register share the same clock source and the same clock enable source from the local interconnect in the associated lab, dedicated i/o clocks, or the column and row interconnects. figure 2?32 shows the ioe in bidirectional configuration. clk_out ce_in clk_in ce_out aclr/preset sclr/preset dedicated i/o clock [5..0] local interconnect local interconnect local interconnect local interconnect local interconnect oe io_coe io_caclr local interconnect io_csclr io_cce_out io_cce_in io_cclk
altera corporation 2?45 october 2003 preliminary i/o structure figure 2?32. cyclone ioe in bidirectional i/o configuration the cyclone device ioe includes programmable delays to ensure zero hold times, minimize setup times, or increase clock to output times. a path in which a pin directly drives a register may require a programmable delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. programmable delays decrea se input-pin-to-logic-array and ioe input register delays. the quartus ii compiler can program these delays chip-wide reset oe register v ccio optional pci clamp column or row interconect ioe_clk[5..0] input register input pin to input register delay or input pin to logic array delay input pin to logic array delay drive strength control open-drain output slew control sclr/preset oe clkout ce_out aclr/prn clkin ce_in output pin delay programmabl e pull-up resistor bus hold prn clrn dq output register prn clrn dq prn clrn dq v ccio comb_datain data_in ena ena ena
2?46 altera corporation preliminary october 2003 cyclone device handbook, volume 1 to automatically minimize setup time while providing a zero hold time. programmable delays can increase the register-to-pin delays for output registers. table 2?9 shows the programmable delays for cyclone devices. there are two paths in the ioe for a co mbinatorial input to reach the logic array. each of the two paths can have a different delay. this allows the designer to adjust delays from the pin to internal le registers that reside in two different areas of the device. the designer sets the two combinatorial input delays by selecting different delays for two different paths under the decrease input delay to internal cells logic option in the quartus ii software. when the input si gnal requires two different delays for the combinatorial input, the input register in the ioe is no longer available. the ioe registers in cyclone devices share the same source for clear or preset. the designer can program preset or clear for each individual ioe. the designer can also program the registers to power up high or low after configuration is complete. if programmed to power up low, an asynchronous clear can control the re gisters. if programmed to power up high, an asynchronous preset can control the registers. this feature prevents the inadvertent activation of another device's active-low input upon power up. if one register in an ioe uses a preset or clear signal then all registers in the ioe must use that same signal if they require preset or clear. additionally a synchronous reset signal is available to the designer for the ioe registers. external ram interfacing cyclone devices support ddr sdram and fcram interfaces at up to 133 mhz through dedicated circuitry. ddr sdram & fcram cyclone devices have dedicated circuitry for interfacing with ddr sdram. all i/o banks support ddr sdram and fcram i/o pins. however, the configuration input pins in bank 1 must operate at 2.5 v because the sstl-2 v ccio level is 2.5 v. additionally, the configuration table 2?9. cyclone programmable delay chain programmable delays quartus ii logic option input pin to logic array delay decrease input delay to internal cells input pin to input register delay decr ease input delay to input registers output pin delay increase delay to output pin
altera corporation 2?47 october 2003 preliminary i/o structure output pins ( nstatus and conf_done ) and all the jtag pins in i/o bank 3 must operate at 2.5 v because the v ccio level of sstl-2 is 2.5 v. i/o banks 1, 2, 3, and 4 support dqs signals with dq bus modes of 8. for 8 mode, there are up to eight groups of programmable dqs and dq pins, i/o banks 1, 2, 3, and 4 each have two groups in the 324-pin and 400-pin fineline bga packages. each group consists of one dqs pin, a set of eight dq pins, and one dm pin (see figure 2?33 ). each dqs pin drives the set of eight dq pins within that group. figure 2?33. cyclone device dq & dqs groups in 8 mode note (1) note to figure 2?33 : (1) each dq group consists of one dqs pin, eight dq pins, and one dm pin. table 2?10 shows the number of dq pin groups per device. dq pins dqs pin dm pin top, bottom, left, or right i/o bank table 2?10. dq pin groups (part 1 of 2) device package number of 8 dq pin groups total dq pin count ep1c3 100-pin tqfp (1) 324 144-pin tqfp 4 32 ep1c4 324-pin fineline bga 8 64 400-pin fineline bga 8 64
2?48 altera corporation preliminary october 2003 cyclone device handbook, volume 1 a programmable delay chain on each dqs pin allows for either a 90 phase shift (for ddr sdram), or a 72 phase shift (for fcram) which automatically center-aligns input dqs synchronization signals within the data window of their corresponding dq data signals. the phase-shifted dqs signals drive the global clock network. this global dqs signal clocks dq signals on internal le registers. these dqs delay elements combine with the pll?s clocking and phase shift ability to provide a complete hardware solution for interfacing to high-speed memory. the clock phase shift allows the pll to clock the dq output enable and output paths. the designer should us e the following guidelines to meet 133 mhz performance for ddr sdram and fcram interfaces: the dqs signal must be in the middle of the dq group it clocks resynchronize the incoming data to the logic array clock using successive le registers or fifo buffers le registers must be placed in the lab adjacent to the dq i/o pin column it is fed by figure 2?34 illustrates ddr sdram and fcram interfacing from the i/o through the dedicated circuitry to the logic array. ep1c6 144-pin tqfp 4 32 240-pin pqfp 4 32 256-pin fineline bga 4 32 ep1c12 240-pin pqfp 4 32 256-pin fineline bga 4 32 324-pin fineline bga 8 64 ep1c20 324-pin fineline bga 8 64 400-pin fineline bga 8 64 note to table 2?10 : (1) ep1c3 devices in the 100-pin tqfp package do not have any dq pin groups in i/o bank 1. table 2?10. dq pin groups (part 2 of 2) device package number of 8 dq pin groups total dq pin count
altera corporation 2?49 october 2003 preliminary i/o structure figure 2?34. ddr sdram & fcram interfacing programmable drive strength the output buffer for each cyclone device i/o pin has a programmable drive strength control for certain i/o standards. the lvttl and lvcmos standards have several levels of drive strength that the designer can control. sstl-3 class i and ii, and sstl-2 class i and ii support a minimum setting, the lowest drive strength that guarantees the i oh /i ol v cc gnd pll phase shifted -90 ? dqs adjacent lab les global clock resynchronizing global clock programmable delay chain output le register output le registers dq input le registers input le registers le register le register ? t adjacent lab les oe oe le register oe le register oe oe le register oe le register output le registers output le register dataa datab clk -90? clk
2?50 altera corporation preliminary october 2003 cyclone device handbook, volume 1 of the standard. using minimum sett ings provides signal slew rate control to reduce system noise and signal overshoot. table 2?11 shows the possible settings for the i/o standa rds with drive strength control. open-drain output cyclone devices provide an optional open-drain (equivalent to an open- collector) output for each i/o pin. this open-drain output enables the device to provide system-level control signals (e.g., interrupt and write- enable signals) that can be asserted by any of several devices. slew-rate control the output buffer for each cyclone device i/o pin has a programmable output slew-rate control that can be configured for low noise or high- speed performance. a faster slew rate provides high-speed transitions for high-performance systems. howe ver, these fast transitions may introduce noise transients into the system. a slow slew rate reduces table 2?11. programmable drive strength i/o standard i oh /i ol current strength setting (ma) lvttl (3.3 v) 4 8 12 16 24 lvcmos (3.3 v) 2 4 8 12 lvttl (2.5 v) 2 8 12 16 lvttl (1.8 v) 2 8 12 lvcmos (1.5 v) 2 4 8
altera corporation 2?51 october 2003 preliminary i/o structure system noise, but adds a nominal delay to rising and falling edges. each i/o pin has an individual slew-rate control, allowing the designer to specify the slew rate on a pin-by-pin basis. the slew-rate control affects both the rising and falling edges. bus hold each cyclone device i/o pin provides an optional bus-hold feature. the bus-hold circuitry can hold the signal on an i/o pin at its last-driven state. since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not necessary to hold a signal level when the bus is tri-stated. the bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. the designer can select this feature individually for each i/o pin. the bus-hold output will drive no higher than v ccio to prevent overdriving signals. if the bus-hold feature is enabled, the device cannot use the programmable pull-up option. disable the bus-hold feature when the i/o pin is configured for differential signals. the bus-hold circuitry uses a resistor with a nominal resistance (rbh) of approximately 7 k ? to pull the signal level to the last-driven state. table 4?15 on page 4?6 gives the specific sustaining current for each v ccio voltage level driven through this resistor and overdrive current used to identify the next-driven input level. the bus-hold circuitry is only active after configuration. when going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. programmable pull-up resistor each cyclone device i/o pin provides an optional programmable pull- up resistor during user mode. if the designer enables this feature for an i/o pin, the pull-up resistor (typically 25 k ? ) holds the output to the v ccio level of the output pin's bank.
2?52 altera corporation preliminary october 2003 cyclone device handbook, volume 1 advanced i/o standard support cyclone device ioes support the following i/o standards: 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos 3.3-v pci lvds sstl-2 class i and ii sstl-3 class i and ii differential sstl-2 class ii (on output clocks only) table 2?12 describes the i/o standards supported by cyclone devices. cyclone devices contain four i/o banks, as shown in figure 2?35 . i/o banks 1 and 3 support all the i/o standards listed in table 2?12 . i/o banks 2 and 4 support all the i/o standards listed in table 2?12 except the 3.3-v pci standard. i/o banks 2 and 4 contain dual-purpose dqs, dq, and dm pins to support a ddr sdra m or fcram interface. i/o bank 1 can also support a ddr sdram or fcram interface, however, the table 2?12. cyclone i/o standards i/o standard type input reference voltage (v ref ) (v) output supply voltage (v ccio ) (v) board termination voltage (v tt ) (v) 3.3-v lvttl/lvcmos single-ended n/a 3.3 n/a 2.5-v lvttl/lvcmos single-ended n/a 2.5 n/a 1.8-v lvttl/lvcmos single-ended n/a 1.8 n/a 1.5-v lvcmos single-ended n/a 1.5 n/a 3.3-v pci (1) single-ended n/a 3.3 n/a lv d s (2) differential n/a 2.5 n/a sstl-2 class i and ii voltage-referenced 1.25 2.5 1.25 sstl-3 class i and ii voltage-referenced 1.5 3.3 1.5 differential sstl-2 (3) differential 1.25 2.5 1.25 notes to table 2?12 : (1) ep1c3 devices support pci by using the lvttl 16-ma i/o standard and drive stre ngth assignments in the quartus ii software. the device requires an external diode for pci compliance. (2) ep1c3 devices in the 100-pin tqfp package do not support the lvds i/o standard. (3) this i/o standard is only available on output clock pins ( pll_out pins).
altera corporation 2?53 october 2003 preliminary i/o structure configuration input pins in i/o bank 1 must operate at 2.5 v. i/o bank 3 can also support a ddr sdram or fc ram interface, however, all the jtag pins in i/o bank 3 must operate at 2.5 v. figure 2?35. cyclone i/o banks notes (1) , (2) notes to figure 2?35 : (1) figure 2?35 is a top view of the silicon die. (2) figure 2?35 is a graphic representation only. refer to the pin list and the quartus ii software for exact pin locations. each i/o bank has its own vccio pins. a single device can support 1.5-v, 1.8-v, 2.5-v, and 3.3-v interfaces; ea ch individual bank can support a different standard with different i/o voltages. each bank also has dual- purpose vref pins to support any one of the voltage-referenced standards (e.g., sstl-3) independently. if an i/o bank does not use voltage-referenced standards, the v ref pins are available as user i/o pins. each i/o bank can support multiple standards with the same v ccio for input and output pins. for example, when v ccio is 3.3-v, a bank can support lvttl, lvcmos, 3.3-v pci, and sstl-3 for inputs and outputs. i/o bank 2 i/o bank 3 i/o bank 4 i/o bank 1 all i/o banks support 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos lvds sstl-2 class i and ii sstl-3 class i and ii i/o bank 3 also support s the 3.3-v pci i/o standard i/o bank 1 also supports the 3.3-v pci i/o standard individual power bus
2?54 altera corporation preliminary october 2003 cyclone device handbook, volume 1 lvds i/o pins a subset of pins in all four i/o banks supports lvds interfacing. these dual-purpose lvds pins require an external-resistor network at the transmitter channels in addition to 100- ? termination resistors on receiver channels. these pins do no t contain dedicated serialization or deserialization circuitry; therefore, internal logic perf orms serialization and deserialization functions. table 2?13 shows the total number of supported lvds channels per device density. multivolt i/o interface the cyclone architecture supports th e multivolt i/o interface feature, which allows cyclone devices in all packages to interface with systems of different supply voltages. the devices have one set of v cc pins for internal operation and input buffers (v ccint ), and four sets for i/o output drivers (v ccio ). the cyclone v ccint pins must always be connected to a 1.5-v power supply. if the v ccint level is 1.5 v, then input pins are 1.5-v, 1.8-v, 2.5-v, and 3.3-v tolerant. the v ccio pins can be connected to either a 1.5-v, 1.8-v, table 2?13. cyclone device lvds channels device pin count number of lvds channels ep1c3 100 (1) 144 34 ep1c4 324 103 400 129 ep1c6 144 29 240 72 256 72 ep1c12 240 66 256 72 324 103 ep1c20 324 95 400 129 note to table 2?13 : (1) ep1c3 devices in the 100-pin tqfp package do not support the lvds i/o standard.
altera corporation 2?55 october 2003 preliminary power sequencing & hot socketing 2.5-v, or 3.3-v power supply, dependin g on the output requirements. the output levels are compatible with systems of the same voltage as the power supply (i.e., when v ccio pins are connected to a 1.5-v power supply, the output levels are compatible with 1.5-v systems). when v ccio pins are connected to a 3.3-v power supply, the output high is 3.3-v and is compatible with 3.3-v or 5.0-v systems. table 2?14 summarizes cyclone multivolt i/o support. power sequencing & hot socketing because cyclone devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. therefore, the v ccio and v ccint power supplies may be powered in any order. signals can be driven into cyclone devices before and during power up without damaging the device. in addition, cyclone devices do not drive out during power up. once operatin g conditions are reached and the device is configured, cyclone devices operate as specified by the user. table 2?14. cyclone multivolt i/o support note (1) v ccio (v) input signal output signal 1.5 v 1.8 v 2.5 v 3.3 v 5.0 v 1.5 v 1.8 v 2.5 v 3.3 v 5.0 v 1.5 vv v (2) v (2) v 1.8 vvv v (3) v 2.5 vv v (5) v (5) v 3.3 v (4) v v (6) v (7) v (7) v (7) v v (8) notes to table 2?14 : (1) the pci clamping diode must be disabled to drive an input with vo ltages higher than v ccio . (2) when v ccio = 1.5-v and a 2.5-v or 3.3-v input signal feeds an input pin, higher pin leakage current is expected. (3) when v ccio = 1.8-v, a cyclone device can drive a 1.5-v device with 1.8-v tolerant inputs. (4) when v ccio = 3.3-v and a 2.5-v input signal feeds an input pin, the v ccio supply current will be slightly larger than expected. (5) when v ccio = 2.5-v, a cyclone device can drive a 1.5-v or 1.8-v device with 2.5-v tolerant inputs. (6) cyclone devices can be 5.0-v tolerant with the use of an external resistor and the internal pci clamp diode. (7) when v ccio = 3.3-v, a cyclone device can drive a 1.5-v, 1.8-v, or 2.5-v device with 3.3-v tolerant inputs. (8) when v ccio = 3.3-v, a cyclone device can drive a device with 5.0-v lvttl inputs but not 5.0-v lvcmos inputs.
2?56 altera corporation preliminary october 2003 cyclone device handbook, volume 1
altera corporation 3?1 may 2003 preliminary 3. configuration & testing ieee std. 1149.1 (jtag) boundary scan support all cyclone devices provide jtag bst circuitry that complies with the ieee std. 1149.1a-1990 spec ification. jtag boundary-scan testing can be performed either before or after, bu t not during configuration. cyclone devices can also use the jtag port fo r configuration together with either the quartus ? ii software or hardware using either jam files ( .jam ) or jam byte-code files ( .jbc ). cyclone devices support reconfiguring the i/o standard settings on the ioe through the jtag bst chain. the jtag chain can update the i/o standard for all input and output pins any time before or during user mode. designers can use this ability for jtag testing before configuration when some of the cyclone pins drive or receive from other devices on the board using voltage-referenced standards. since the cyclone device might not be configured before jtag testing, the i/o pins might not be configured for appropriate electrical standards for chip-to-chip communication. programming those i/o standards via jtag allows designers to fully test i/o connection to other devices. the jtag pins support 1.5-v/1.8-v or 2.5-v/3.3-v i/o standards. the tdo pin voltage is determined by the v ccio of the bank where it resides. the bank v ccio selects whether the jtag inputs are 1.5-v, 1.8-v, 2.5-v, or 3.3-v compatible. cyclone devices also use the jtag port to monitor the operation of the device with the signaltap ? ii embedded logic analyzer. cyclone devices support the jtag instructions shown in table 3?1 . table 3?1. cyclone jtag instructions (part 1 of 2) jtag instruction instruction code description sample / preload 00 0000 0101 allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. also used by the signaltap ii embedded logic analyzer. extest (1) 00 0000 0000 allows the external circui try and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass 11 1111 1111 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation. c51003-1.0
3?2 altera corporation preliminary may 2003 cyclone device handbook, volume 1 usercode 00 0000 0111 selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the userco de to be serially shifted out of tdo . idcode 00 0000 0110 selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . highz (1) 00 0000 1011 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the i/o pins. clamp (1) 00 0000 1010 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices duri ng normal device operation while holding i/o pins to a state defined by the data in the boundary-scan register. icr instructions used when configuring a cyclone device via the jtag port with a masterblaster tm or byteblastermv tm download cable, or when using a jam file or jam byte-code file via an embedded processor. pulse_nconfig 00 0000 0001 emulates pulsing the nconfig pin low to trigger reconfiguration even though the physical pin is unaffected. config_io 00 0000 1101 allows configuration of i/o standards through the jtag chain for jtag testing. can be executed before, after, or during configuration. stops configuration if executed during configuration. once issued, the config_io instruction will hold nstatus low to reset the configuration device. nstatus is held low until the device is reconfigured. signaltap ii instructions monitors internal device operati on with the signaltap ii embedded logic analyzer. note to ta b l e 3 ? 1 : (1) bus hold and weak pull-up resistor features override the high-impedance state of highz , clamp , and extest . table 3?1. cyclone jtag instructions (part 2 of 2) jtag instruction instruction code description
altera corporation 3?3 may 2003 preliminary ieee std. 1149.1 (jtag) boundary scan support the cyclone device instruction register length is 10 bits and the usercode register length is 32 bits. tables 3?2 and 3?3 show the boundary-scan register length and device idcode information for cyclone devices. table 3?2. cyclone boundary-scan register length device boundary-scan register length ep1c3 339 ep1c4 930 ep1c6 582 ep1c12 774 ep1c20 930 table 3?3. 32-bit cyclone device idcode device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) (2) ep1c3 0000 0010 0000 1000 0001 000 0110 1110 1 ep1c4 0000 0010 0000 1000 0101 000 0110 1110 1 ep1c6 0000 0010 0000 1000 0010 000 0110 1110 1 ep1c12 0000 0010 0000 1000 0011 000 0110 1110 1 ep1c20 0000 0010 0000 1000 0100 000 0110 1110 1 notes to ta b l e 3 ? 3 : (1) the most significant bit (msb) is on the left. (2) the idcode?s least significant bit (lsb) is always 1 .
3?4 altera corporation preliminary may 2003 cyclone device handbook, volume 1 figure 3?1 shows the timing requirements for the jtag signals. figure 3?1. cyclone jtag waveforms table 3?4 shows the jtag timing parameters and values for cyclone devices. table 3?4. cyclone jtag timing parameters & values symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 35 ns t jszx update register high impedance to valid output 35 ns t jsxz update register valid output to high impedance 35 ns tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz
altera corporation 3?5 may 2003 preliminary signaltap ii embedded logic analyzer f for more information on jtag , see the following documents: an 39: ieee std. 1149.1 (jtag) boun dary-scan testing in altera devices jam programming & test language specification signaltap ii embedded logic analyzer cyclone devices feature the signaltap ii embedded logic analyzer, which monitors design operation over a period of time through the ieee std. 1149.1 (jtag) circuitry. a designer can analyze internal logic at speed without bringing internal signals to the i/o pins. this feature is particularly important for advanced packages, such as fineline bga packages, because it can be difficult to add a connection to a pin during the debugging process after a boar d is designed and manufactured. configuration the logic, circuitry, and interconnects in the cyclone architecture are configured with cmos sram elements. cyclone devices are reconfigurable and are 100% tested prior to shipment. as a result, the designer does not have to generate test vectors for fault coverage purposes, and can instead focus on simulation and design verification. in addition, the designer does not need to manage inventories of different asic designs. cyclone devices can be configured on the board for the specific functionality required. cyclone devices are configured at system power-up with data stored in an altera configuration device or provided by a system controller. the cyclone device's optimized interface allows the device to act as controller in an active serial configuration sc heme with the new low-cost serial configuration device. cyclone devices can be configured in under 120 ms using serial data at 20 mhz. the serial configuration device can be programmed via the byteblaster ii download cable, the altera programming unit (apu), or third-party programmers. in addition to the new low-cost serial configuration device, altera offers in-system programmability (isp)-capab le configuration devices that can configure cyclone devices via a serial data stream. the interface also enables microprocessors to treat cyclone devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. after a cyclone device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. real-time changes can be made during system operation, enabling innovative reconfigurable computing applications.
3?6 altera corporation preliminary may 2003 cyclone device handbook, volume 1 operating modes the cyclone architecture uses sram configuration elements that require configuration data to be loaded ea ch time the circuit powers up. the process of physically loading the sram data into the device is called configuration. during initializatio n, which occurs immediately after configuration, the device resets registers, enables i/o pins, and begins to operate as a logic device. together, the configuration and initialization processes are called command mode. normal device operation is called user mode. sram configuration elements allow cyclone devices to be reconfigured in-circuit by loading new configuratio n data into the device. with real- time reconfiguration, the device is forced into command mode with a device pin. the configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. designers can perform in-field upgrades by distribu ting new configuration files either within the system or remotely. a built-in weak pull-up resistor pulls all user i/o pins to v ccio before and during device configuration. the configuration pins support 1.5-v/1.8-v or 2.5-v/3.3-v i/o standards. the voltage level of the configuration output pins is determined by the v ccio of the bank where the pins reside. the bank v ccio selects whether the configuration inputs are 1.5-v, 1.8-v, 2.5-v, or 3.3-v compatible. configuration schemes designers can load the configuration data for a cyclone device with one of three configuration schemes (see table 3?5 ), chosen on the basis of the target application. designers can use a configuration device, intelligent controller, or the jtag port to configure a cyclone device. a low-cost configuration device can automatically configure a cyclone device at system power-up.
altera corporation 3?7 may 2003 preliminary configuration multiple cyclone devices can be configured in any of the three configuration schemes by connect ing the configuration enable ( nce ) and configuration enable output ( nceo ) pins on each device. table 3?5. data sources for configuration configuration scheme data source active serial low-cost serial configuration device passive serial (ps) enhanced or epc2 configuration device, masterblaster or byteblastermv download cable, or serial data source jtag masterblaster or byteblastermv download cable or a microprocessor with a jam or jbc file
3?8 altera corporation preliminary may 2003 cyclone device handbook, volume 1
altera corporation 4?1 january 2004 preliminary 4. dc & switching characteristics operating conditions cyclone devices are offered in both commercial, industrial, and extended temperature grades. however, in dustrial-grade and extended- temperature-grade devices may have limited speed-grade availability. tables 4?1 through 4?16 provide information on absolute maximum ratings, recommended operating cond itions, dc operating conditions, and capacitance for cyclone devices. table 4?1. cyclone device absolute maximum ratings notes (1) , (2) symbol parameter conditions minimum maximum unit v ccint supply voltage with respect to ground (3) ?0.5 2.4 v v ccio ?0.5 4.6 v v i dc input voltage ?0.5 4.6 v i out dc output current, per pin ?25 25 ma t stg storage temperature no bias ?65 150 c t amb ambient temperature under bias ?65 135 c t j junction temperature bga packages under bias 135 c table 4?2. cyclone device recommended operating conditions (part 1 of 2) symbol parameter conditions minimum maximum unit v ccint supply voltage for internal logic and input buffers (4) 1.425 1.575 v v ccio supply voltage for output buffers, 3.3-v operation (4) 3.00 3.60 v supply voltage for output buffers, 2.5-v operation (4) 2.375 2.625 v supply voltage for output buffers, 1.8-v operation (4) 1.71 1.89 v supply voltage for output buffers, 1.5-v operation (4) 1.4 1.6 v v i input voltage (3) , (5) ?0.5 4.1 v c51004-1.3
4?2 altera corporation preliminary january 2004 cyclone device handbook, volume 1 v o output voltage 0 v ccio v t j operating junction temperature for commercial use 085 c for industrial use ?40 100 c for extended- temperature use ?40 125 c t r input rise time 40 ns t f input fall time 40 ns table 4?3. cyclone device dc operating conditions note (6) symbol parameter conditions minimum typical maximum unit i i input pin leakage current v i = v cciomax to 0 v (8) ?10 10 a i oz tri-stated i/o pin leakage current v o = v cciomax to 0 v (8) ?10 10 a i cc0 v cc supply current (standby) (all m4k blocks in power- down mode) (7) ep1c3 4 ma ep1c4 6 ma ep1c6 6 ma ep1c12 8 ma ep1c20 12 ma r conf value of i/o pin pull- up resistor before and during configuration v ccio = 3.0 v (9) 20 50 k ? v ccio = 2.375 v (9) 30 80 k ? v ccio = 1.71 v (9) 60 150 k ? table 4?4. lvttl specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage i oh = ?4 to ?24 ma (10) 2.4 v v ol low-level output voltage i ol = 4 to 24 ma (10) 0.45 v table 4?2. cyclone device recommended operating conditions (part 2 of 2) symbol parameter conditions minimum maximum unit
altera corporation 4?3 january 2004 preliminary operating conditions table 4?5. lvcmos specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage v ccio = 3.0, i oh = ?0.1 ma v ccio ? 0.2 v v ol low-level output voltage v ccio = 3.0, i ol = 0.1 ma 0.2 v table 4?6. 2.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 2.375 2.625 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage i oh = ?0.1 ma 2.1 v i oh = ?1 ma 2.0 v i oh = ?2 to ?16 ma (10) 1.7 v v ol low-level output voltage i ol = 0.1 ma 0.2 v i oh = 1 ma 0.4 v i oh = 2 to 16 ma (10) 0.7 v table 4?7. 1.8-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 1.65 1.95 v v ih high-level input voltage 0.65 v ccio 2.25 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 to ?8 ma (10) v ccio ? 0.45 v v ol low-level output voltage i ol = 2 to 8 ma (10) 0.45 v
4?4 altera corporation preliminary january 2004 cyclone device handbook, volume 1 table 4?8. 1.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 1.4 1.6 v v ih high-level input voltage 0.65 v ccio v ccio + 0.3 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (10) 0.75 v ccio v v ol low-level output voltage i ol = 2 ma (10) 0.25 v ccio v table 4?9. 2.5-v lvds i/o specifications note (11) symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 2.375 2.5 2.625 v v od differential output voltage r l = 100 ? 250 550 mv ? v od change in v od between high and low r l = 100 ? 50 mv v os output offset voltage r l = 100 ? 1.125 1.25 1.375 v ? v os change in v os between high and low r l = 100 ? 50 mv v th differential input threshold v cm = 1.2 v ?100 100 mv v in receiver input voltage range 0.0 2.4 v r l receiver differential input resistor 90 100 110 ? table 4?10. 3.3-v pci specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.5 0.3 v ccio v v oh high-level output voltage i out = ?500 a0.9 v ccio v v ol low-level output voltage i out = 1,500 a0.1 v ccio v
altera corporation 4?5 january 2004 preliminary operating conditions table 4?11. sstl-2 class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.15 1.25 1.35 v v ih high-level input voltage v ref + 0.18 3.0 v v il low-level input voltage ?0.3 v ref ? 0.18 v v oh high-level output voltage i oh = ?8.1 ma (10) v tt + 0.57 v v ol low-level output voltage i ol = 8.1 ma (10) v tt ? 0.57 v table 4?12. sstl-2 class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.3 2.5 2.7 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.15 1.25 1.35 v v ih high-level input voltage v ref + 0.18 v ccio + 0.3 v v il low-level input voltage ?0.3 v ref ? 0.18 v v oh high-level output voltage i oh = ?16.4 ma (10) v tt + 0.76 v v ol low-level output voltage i ol = 16.4 ma (10) v tt ? 0.76 v table 4?13. sstl-3 class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v tt termination voltage v ref ? 0.05 v ref v ref + 0.05 v v ref reference voltage 1.3 1.5 1.7 v v ih high-level input voltage v ref + 0.2 v ccio + 0.3 v v il low-level input voltage ?0.3 v ref ? 0.2 v v oh high-level output voltage i oh = ?8 ma (10) v tt + 0.6 v v ol low-level output voltage i ol = 8 ma (10) v tt ? 0.6 v
4?6 altera corporation preliminary january 2004 cyclone device handbook, volume 1 table 4?14. sstl-3 class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v tt termination voltage v ref ? 0.05 v ref v ref + 0.05 v v ref reference voltage 1.3 1.5 1.7 v v ih high-level input voltage v ref + 0.2 v ccio + 0.3 v v il low-level input voltage ?0.3 v ref ? 0.2 v v oh high-level output voltage i oh = ?16 ma (10) v tt + 0.8 v v ol low-level output voltage i ol = 16 ma (10) v tt ? 0.8 v table 4?15. bus hold parameters parameter conditions v ccio level unit 1.5 v 1.8 v 2.5 v 3.3 v min max min max min max min max low sustaining current v in > v il (maximum) 30 50 70 a high sustaining current v in < v ih (minimum) ?30 ?50 ?70 a low overdrive current 0 v < v in < v ccio 200 300 500 a high overdrive current 0 v < v in < v ccio ?200 ?300 ?500 a
altera corporation 4?7 january 2004 preliminary operating conditions table 4?16. cyclone device capacitance note (12) symbol parameter typical unit c io input capacitance for user i/o pin 4.0 pf c lv d s input capacitance for dual-pur pose lvds/user i/o pin 4.7 pf c vref input capacitance for dual-purpose v ref /user i/o pin. 12.0 pf c dpclk input capacitance for dual-purpose dpclk /user i/o pin. 4.4 pf c clk input capacitance for clk pin. 4.7 pf notes to ta b l e s 4 ? 1 through 4?16 : (1) see the operating requirements for altera devices data sheet . (2) conditions beyond those listed in table 4?1 may cause permanent damage to a device. additionally, device operation at the absolute maximum ratings for extended pe riods of time may have adve rse affects on the device. (3) minimum dc input is ?0.5 v. during transitions, the in puts may undershoot to ?0.5 v or overshoot to 4.6 v for input currents less than 100 ma and periods shorter than 20 ns. (4) maximum v cc rise time is 100 ms, and v cc must rise monotonically. (5) all pins, including dedicated inputs, clock, i/o, and jtag pins, may be driven before v ccint and v ccio are powered. (6) typical values are for t a = 25 c, v ccint = 1.5 v, and v ccio = 1.5 v, 1.8 v, 2.5 v, and 3.3 v. (7) v i = ground, no load, no toggling inputs. (8) this value is specified for normal device operation. the value may vary during power-up. this applies for all v ccio settings (3.3, 2.5, 1.8, and 1.5 v). (9) pin pull-up resistance values will lower if an external source drives the pin higher than v ccio . (10) drive strength is programmable according to values in table 4?14 . (11) the cyclone lvds interface requires a resist or network outside of the transmitter channels. (12) capacitance is sample-tested only. capacitance is me asured using time-domain reflections (tdr). measurement accuracy is within 0.5 pf.
4?8 altera corporation preliminary january 2004 cyclone device handbook, volume 1 power consumption designers can use the altera web power calculator to estimate the device power. cyclone devices require a certain amount of power-up current to successfully power up because of the nature of the leading-edge process on which they are fabricated. table 4?17 shows the maximum power-up current required to power up a cyclone device. designers should select power supplies and regulators that can supply this amount of current when designing with cyclone devices. this specification is for commercial operating conditions. measurements were performed with an isolated cyclone device on the board. decoupling capacitors were not used in this meas urement. to factor in the current for decoupling capacitors, sum up the current for each capacitor using the following equation: i = c (dv/dt) the exact amount of current that will be consumed varies according to the process, temperature, and power ra mp rate. if the power supply or regulator can supply more current than required, the cyclone device may consume more current than the maximum current specified in table 4?17 . however, the device does not require any more current to successfully power up than what is listed in table 4?17 . table 4?17. cyclone power-up current (i ccint ) requirements device maximum power-up current requirement unit ep1c3 300 ma ep1c4 (1) 400 ma ep1c6 (2) 500 ma ep1c12 900 ma ep1c20 1,200 ma notes to ta b l e 4 ? 1 7 : (1) the ep1c4 maximum power-up current is an estimated specification and may change. (2) the ep1c6 maximum power-up current is for all ep1c6 devices except for those with lot codes listed in the cyclone fpga family errata sheet .
altera corporation 4?9 january 2004 preliminary timing model the duration of the i ccint power-up requirement depends on the v ccint voltage supply rise time. the power-up current consumption drops when the v ccint supply reaches approximately 0. 75 v. for example, if the v ccint rise time has a linear rise of 15 ms, the current consumption spike will drop by 7.5 ms. typically, the user-mode current duri ng device operation is lower than the power-up current in table 4?17 . altera recommends using the cyclone power calculator, available on the altera web site, to estimate the user-mode i ccint consumption and then select power supplies or regulators based on the higher value. timing model the directdrive technology and mu ltitrack interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all cyclone device densities and speed grades. this section describes and specifies the pe rformance, internal, external, and pll timing specifications. all specifications are representative of worst-case supply voltage and junction temperature conditions. preliminary & final timing timing models can have either preliminary or final status. the quartus ? ii software issues an informat ional message during the design compilation if the timing models are preliminary. table 4?18 shows the status of the cyclone device timing models. preliminary status means the timing mo del is subject to change. initially, timing numbers are created using simulation results, process data, and other known parameters. these tests are used to make the preliminary numbers as close to the actual timing parameters as possible. final timing numbers are based on ac tual device operation and testing. these numbers reflect the actual perf ormance of the device under worst- case voltage and junction temperature conditions.
4?10 altera corporation preliminary january 2004 cyclone device handbook, volume 1 performance the maximum internal logic array clock tree frequency is limited to the specifications shown in table 4?19 . table 4?18. cyclone device timing model status device preliminary final ep1c3 v ep1c4 v ep1c6 v ep1c12 v ep1c20 v table 4?19. clock tree maximum performance specification parameter definition -6 speed grade -7 speed grade -8 speed grade units min typ max min typ max min typ max clock tree f max maximum frequency that the clock tree can support for clocking registered logic 405 320 275 mhz
altera corporation 4?11 january 2004 preliminary timing model table 4?20 shows the cyclone device performance for some common designs. all performance values were obtained with the quartus ii software compilation of library of parameterized modules (lpm) functions or megafunctions. these performance values are based on ep1c6 devices in 144-p in tqfp packages. internal timing parameters internal timing parame ters are specified on a speed grade basis independent of device density. tables 4?21 through 4?24 describe the cyclone device internal timing microparameters for les, ioes, m4k memory structures, and multitrack interconnects. table 4?20. cyclone device performance resource used design size & function mode resources used performance les m4k memory bits m4k memory blocks -6 speed grade (mhz) -7 speed grade (mhz) -8 speed grade (mhz) le 16-to-1 multiplexer - 21 - - 405.00 320.00 275.00 32-to-1 multiplexer - 44 - - 317.36 284.98 260.15 16-bit counter - 16 - - 405.00 320.00 275.00 64-bit counter (1) - 66 - - 208.99 181.98 160.75 m4k memory block ram 128 36 bit single port - 4,608 1 256.00 222.67 197.01 ram 128 36 bit simple dual-port mode - 4,608 1 255.95 222.67 196.97 ram 256 18 bit true dual- port mode - 4,608 1 255.95 222.67 196.97 fifo 128 36 bit - 40 4,608 1 256.02 222.67 197.01 shift register 94128 shift register 11 4,536 1 255.95 222.67 196.97 note to table 4?20 : (1) the performance numbers for this function are from an ep1c6 device in a 240-pin pqfp package. table 4?21. le internal timing microparameter descriptions (part 1 of 2) symbol parameter t su le register setup time before clock t h le register hold time after clock
4?12 altera corporation preliminary january 2004 cyclone device handbook, volume 1 t co le register clock-to-output delay t lut le combinatorial lut delay for data-in to data-out t clr minimum clear pulse width t pre minimum preset pulse width t clkhl minimum clock high or low time table 4?22. ioe internal timing microparameter descriptions symbol parameter t su ioe input and output register setup time before clock t h ioe input and output register hold time after clock t co ioe input and output register clock-to-output delay t pin2combout_r row input pin to ioe combinatorial output t pin2combout_c column input pin to ioe combinatorial output t combin2pin_r row ioe data input to combinatorial output pin t combin2pin_c column ioe data input to combinatorial output pin t clr minimum clear pulse width t pre minimum preset pulse width t clkhl minimum clock high or low time table 4?21. le internal timing microparameter descriptions (part 2 of 2) symbol parameter
altera corporation 4?13 january 2004 preliminary timing model table 4?23. m4k block internal timing microparameter descriptions symbol parameter t m4krc synchronous read cycle time t m4kwc synchronous write cycle time t m4kweresu write or read enable setup time before clock t m4kwereh write or read enable hold time after clock t m4kbesu byte enable setup time before clock t m4kbeh byte enable hold time after clock t m4kdataasu a port data setup time before clock t m4kdataah a port data hold time after clock t m4kaddrasu a port address setup time before clock t m4kaddrah a port address hold time after clock t m4kdatabsu b port data setup time before clock t m4kdatabh b port data hold time after clock t m4kaddrbsu b port address setup time before clock t m4kaddrbh b port address hold time after clock t m4kdataco1 clock-to-output delay when using output registers t m4kdataco2 clock-to-output delay without output registers t m4kclkhl minimum clock high or low time t m4kclr minimum clear pulse width table 4?24. routing delay internal timing microparameter descriptions symbol parameter t r4 delay for an r4 line with average loading; covers a distance of four lab columns t c4 delay for an c4 line with average loading; covers a distance of four lab rows t local local interconnect delay
4?14 altera corporation preliminary january 2004 cyclone device handbook, volume 1 figure 4?1 shows the memory waveforms fo r the m4k timing parameters shown in table 4?23 . figure 4?1. dual-port ram timing microparameter waveform internal timing parame ters are specified on a speed grade basis independent of device density. tables 4?25 through 4?28 show the internal timing microparameters for les, ioes, trimatrix memory structures, dsp blocks, and multitrack interconnects. wrclock wren wraddress data-in reg_data-out an-1 an a0 a1 a2 a3 a4 a5 din-1 din din4 din5 rdclock a6 din6 unreg_data-out rden rdaddress bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 t weresu t wereh t datac o 1 t datac o 2 t datasu t data h t wereh t weresu t waddrsu t waddrh dout0 t rc table 4?25. le internal timing microparameters (part 1 of 2) symbol -6 -7 -8 unit minmaxminmaxminmax t su 29 33 37 ps t h 12 13 15 ps t co 173 198 224 ps t lut 454 522 590 ps
altera corporation 4?15 january 2004 preliminary timing model t clr 129 148 167 ps t pre 129 148 167 ps t clkhl 107 123 139 ps table 4?26. ioe internal timing microparameters symbol -6 -7 -8 unit minmaxminmaxminmax t su 348 400 452 ps t h 000ps t co 511 587 664 ps t pin2combout_r 1,130 1,299 1,469 ps t pin2combout_c 1,135 1,305 1,475 ps t combin2pin_r 2,627 3,021 3,415 ps t combin2pin_c 2,615 3,007 3,399 ps t clr 280 322 364 ps t pre 280 322 364 ps t clkhl 95 109 123 ps table 4?27. m4k block internal timing microparameters (part 1 of 2) symbol -6 -7 -8 unit minmaxminmaxminmax t m4krc 4,379 5,035 5,691 ps t m4kwc 2,910 3,346 3,783 ps t m4kweresu 72 82 93 ps t m4kwereh 43 49 55 ps t m4kbesu 72 82 93 ps t m4kbeh 43 49 55 ps t m4kdataasu 72 82 93 ps t m4kdataah 43 49 55 ps table 4?25. le internal timing microparameters (part 2 of 2) symbol -6 -7 -8 unit minmaxminmaxminmax
4?16 altera corporation preliminary january 2004 cyclone device handbook, volume 1 external timing parameters external timing parameters are specified by device density and speed grade. figure 4?2 shows the timing model for bidirectional ioe pin timing. all registers are within the ioe. t m4kaddrasu 72 82 93 ps t m4kaddrah 43 49 55 ps t m4kdatabsu 72 82 93 ps t m4kdatabh 43 49 55 ps t m4kaddrbsu 72 82 93 ps t m4kaddrbh 43 49 55 ps t m4kdataco1 621 714 807 ps t m4kdataco2 4,351 5,003 5,656 ps t m4kclkhl 105 120 136 ps t m4kclr 286 328 371 ps table 4?28. routing delay internal timing microparameters symbol -6 -7 -8 unit minmaxminmaxminmax t r4 261 300 339 ps t c4 338 388 439 ps t local 244 281 318 ps table 4?27. m4k block internal timing microparameters (part 2 of 2) symbol -6 -7 -8 unit minmaxminmaxminmax
altera corporation 4?17 january 2004 preliminary timing model figure 4?2. external timing in cyclone devices all external i/o timing parameters shown are for 3.3-v lvttl i/o standard with the maximum current strength and fast slew rate. for external i/o timing using standards other than lvttl or for different current strengths, use the i/o standard input and output delay adders in tables 4?40 through 4?44 . table 4?29 shows the external i/o timing parameters when using global clock networks. prn clrn dq prn clrn dq prn clrn dq dedicated clock bidirectional pin output register input register oe register t xz t zx t insu t inh t outco table 4?29. cyclone global clock ex ternal i/o timing parameters notes (1) , (2) (part 1 of 2) symbol parameter conditions t insu setup time for input or bidi rectional pin using ioe input register with global clock fed by clk pin t inh hold time for input or bidi rectional pin using ioe input register with global clock fed by clk pin t outco clock-to-output delay output or bidirectional pin using ioe output register with global clock fed by clk pin c load = 10 pf t xz synchronous column ioe output enable register to output pin disable delay using global clock fed by clk pin c load = 10 pf t zx synchronous column ioe output enable register to output pin enable delay using global clock fed by clk pin c load = 10 pf t insupll setup time for input or bidi rectional pin using ioe input register with global clock fed by enhanced pll with default phase setting
4?18 altera corporation preliminary january 2004 cyclone device handbook, volume 1 tables 4?30 through 4?31 show the external timing parameters on column and row pins for ep1c3 devices. t inhpll hold time for input or bidi rectional pin using ioe input register with global clock fed by enhanced pll with default phase setting t outcopll clock-to-output delay output or bidirectional pin using ioe output register with global clock enhanced pll with default phase setting c load = 10 pf t xzpll synchronous column ioe output enable register to output pin disable delay using global clock fed by enhanced pll with default phase setting c load = 10 pf t zxpll synchronous column ioe output enable register to output pin enable delay using global clock fed by enhanced pll with default phase setting c load = 10 pf notes to table 4?29 : (1) these timing parameters are sample-tested only. (2) these timing parameters are for ioe pins using a 3.3-v lvttl, 24-ma setting. design ers should use the quartus ii software to verify the external timing for any pin. table 4?29. cyclone global clock ex ternal i/o timing parameters notes (1) , (2) (part 2 of 2) symbol parameter conditions table 4?30. ep1c3 column pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t insu 3.085 3.547 4.009 ns t inh 0.000 0.000 0.000 ns t outco 2.000 4.073 2.000 4.682 2.000 5.295 ns t xz 4.035 4.638 5.245 ns t zx 4.035 4.638 5.245 ns t insupll 1.795 2.063 2.332 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.306 0.500 2.651 0.500 2.998 ns t xzpll 2.268 2.607 2.948 ns t zxpll 2.268 2.607 2.948 ns
altera corporation 4?19 january 2004 preliminary timing model tables 4?32 through 4?33 show the external timing parameters on column and row pins for ep1c4 devices. table 4?31. ep1c3 row pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t insu 3.157 3.630 4.103 ns t inh 0.000 0.000 0.000 ns t outco 2.000 3.984 2.000 4.580 2.000 5.180 ns t xz 3.905 4.489 5.077 ns t zx 3.905 4.489 5.077 ns t insupll 1.867 2.146 2.426 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.217 0.500 2.549 0.500 2.883 ns t xzpll 2.138 2.458 2.780 ns t zxpll 2.138 2.458 2.780 ns table 4?32. ep1c4 column pin global clock external i/o timing parameters note (1) symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t insu 2.671 3.071 3.470 ns t inh 0.000 0.000 0.000 ns t outco 2.000 3.937 2.000 4.526 2.000 5.119 ns t xz 3.899 4.482 5.069 ns t zx 3.899 4.482 5.069 ns t insupll 1.471 1.690 1.910 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.080 0.500 2.392 0.500 2.705 ns t xzpll 2.042 2.348 2.655 ns t zxpll 2.042 2.348 2.655 ns
4?20 altera corporation preliminary january 2004 cyclone device handbook, volume 1 tables 4?34 through 4?35 show the external timing parameters on column and row pins for ep1c6 devices. table 4?33. ep1c4 row pin global clock external i/o timing parameters note (1) symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t insu 2.800 3.220 3.639 ns t inh 0.000 0.000 0.000 ns t outco 2.000 3.791 2.000 4.358 2.000 4.929 ns t xz 3.712 4.267 4.826 ns t zx 3.712 4.267 4.826 ns t insupll 1.600 1.839 2.079 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 1.934 0.500 2.224 0.500 2.515 ns t xzpll 1.855 2.133 2.412 ns t zxpll 1.855 2.133 2.412 ns note to tables 4?32 and 4?33 : (1) contact altera applications fo r ep1c4 device timing parameters. table 4?34. ep1c6 column pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t insu 2.691 3.094 3.496 ns t inh 0.000 0.000 0.000 ns t outco 2.000 3.917 2.000 4.503 2.000 5.093 ns t xz 3.879 4.459 5.043 ns t zx 3.879 4.459 5.043 ns t insupll 1.513 1.739 1.964 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.038 0.500 2.343 0.500 2.651 ns t xzpll 2.000 2.299 2.601 ns t zxpll 2.000 2.299 2.601 ns
altera corporation 4?21 january 2004 preliminary timing model tables 4?36 through 4?37 show the external timing parameters on column and row pins for ep1c12 devices. table 4?35. ep1c6 row pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t insu 2.774 3.190 3.605 ns t inh 0.000 0.000 0.000 ns t outco 2.000 3.817 2.000 4.388 2.000 4.963 ns t xz 3.738 4.297 4.860 ns t zx 3.738 4.297 4.860 ns t insupll 1.596 1.835 2.073 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 1.938 0.500 2.228 0.500 2.521 ns t xzpll 1.859 2.137 2.418 ns t zxpll 1.859 2.137 2.418 ns table 4?36. ep1c12 column pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t insu 2.510 2.885 3.259 ns t inh 0.000 0.000 0.000 ns to utco 2.000 3.798 2.000 4.367 2.000 4.940 ns t xz 3.760 4.323 4.890 ns t zx 3.760 4.323 4.890 ns t insupll 1.588 1.824 2.061 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 1.663 0.500 1.913 0.500 2.164 ns t xzpll 1.625 1.869 2.114 ns t zxpll 1.625 1.869 2.114 ns
4?22 altera corporation preliminary january 2004 cyclone device handbook, volume 1 tables 4?38 through 4?39 show the external timing parameters on column and row pins for ep1c20 devices. table 4?37. ep1c12 row pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t insu 2.620 3.012 3.404 ns t inh 0.000 0.000 0.000 ns t outco 2.000 3.671 2.000 4.221 2.000 4.774 ns t xz 3.592 4.130 4.671 ns t zx 3.592 4.130 4.671 ns t insupll 1.698 1.951 2.206 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 1.536 0.500 1.767 0.500 1.998 ns t xzpll 1.457 1.676 1.895 ns t zxpll 1.457 1.676 1.895 ns table 4?38. ep1c20 column pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t insu 2.288 2.630 2.971 ns t inh 0.000 0.000 0.000 ns t outco 2.000 3.870 2.000 4.450 2.000 5.033 ns t xz 3.832 4.406 4.983 ns t zx 3.832 4.406 4.983 ns t insupll 1.288 1.480 1.671 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 1.813 0.500 2.085 0.500 2.359 ns t xzpll 1.775 2.041 2.309 ns t zxpll 1.775 2.041 2.309 ns
altera corporation 4?23 january 2004 preliminary timing model external i/o delay parameters external i/o delay timing parameters for i/o standard input and output adders and programmable input and output delays are specified by speed grade independent of device density. tables 4?40 through 4?45 show the adder delays associated with column and row i/o pins for all packages. if an i/o standard is selected other than lvttl 24 ma with a fast slew rate, add the selected delay to the external t co and t su i/o parameters shown in tables 4?25 through 4?28 . table 4?39. ep1c20 row pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t insu 2.417 2.779 3.140 ns t inh 0.000 0.000 0.000 ns t outco 2.000 3.724 2.000 4.282 2.000 4.843 ns t xz 3.645 4.191 4.740 ns t zx 3.645 4.191 4.740 ns t insupll 1.417 1.629 1.840 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 1.667 0.500 1.917 0.500 2.169 ns t xzpll 1.588 1.826 2.066 ns t zxpll 1.588 1.826 2.066 ns table 4?40. cyclone i/o standard column pin input delay adders (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max lvcmos 000ps 3.3-v lvttl 0 0 0 ps 2.5-v lvttl 27 31 35 ps 1.8-v lvttl 182 209 236 ps 1.5-v lvttl 278 319 361 ps sstl-3 class i ? 250 ? 288 ? 325 ps sstl-3 class ii ? 250 ? 288 ? 325 ps sstl-2 class i ? 278 ? 320 ? 362 ps
4?24 altera corporation preliminary january 2004 cyclone device handbook, volume 1 sstl-2 class ii ? 278 ? 320 ? 362 ps lv d s ? 261 ? 301 ? 340 ps table 4?41. cyclone i/o standard row pin input delay adders i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max lvcmos 000ps 3.3-v lvttl 0 0 0 ps 2.5-v lvttl 27 31 35 ps 1.8-v lvttl 182 209 236 ps 1.5-v lvttl 278 319 361 ps 3.3-v pci (1) 000ps sstl-3 class i ? 250 ? 288 ? 325 ps sstl-3 class ii ? 250 ? 288 ? 325 ps sstl-2 class i ? 278 ? 320 ? 362 ps sstl-2 class ii ? 278 ? 320 ? 362 ps lv d s ? 261 ? 301 ? 340 ps table 4?42. cyclone i/o standard output delay adders for fast slew rate on column pins (part 1 of 2) standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max lvcmos 2 ma 993 1,142 1,291 ps 4 ma 504 579 655 ps 8 ma 138 158 179 ps 12 ma 0 0 0 ps 3.3-v lvttl 4 ma 993 1,142 1,291 ps 8 ma 646 742 839 ps 12 ma 135 155 175 ps 16 ma 174 200 226 ps 24 ma 0 0 0 ps table 4?40. cyclone i/o standard column pin input delay adders (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max
altera corporation 4?25 january 2004 preliminary timing model 2.5-v lvttl 2 ma 1,322 1,520 1,718 ps 8 ma 332 381 431 ps 12 ma 338 388 439 ps 16 ma 198 227 257 ps 1.8-v lvttl 2 ma 997 1,146 1,296 ps 8 ma 785 902 1,020 ps 12 ma 785 902 1,020 ps 1.5-v lvttl 2 ma 3,281 3,773 4,265 ps 4 ma 1,601 1,841 2,081 ps 8 ma 1,285 1,477 1,670 ps sstl-3 class i 583 670 758 ps sstl-3 class ii 182 209 236 ps sstl-2 class i 508 584 660 ps sstl-2 class ii 235 270 305 ps lv d s ? 5 ? 6 ? 7ps table 4?43. cyclone i/o standard output delay adders for fast slew rate on row pins (part 1 of 2) standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max lvcmos 2 ma 993 1,142 1,291 ps 4 ma 504 579 655 ps 8 ma 138 158 179 ps 12 ma 0 0 0 ps 3.3-v lvttl 4 ma 993 1,142 1,291 ps 8 ma 646 742 839 ps 12 ma 135 155 175 ps 16 ma 174 200 226 ps 24 ma 0 0 0 ps 2.5-v lvttl 2 ma 1,322 1,520 1,718 ps 8 ma 332 381 431 ps 12 ma 338 388 439 ps 16 ma 198 227 257 ps table 4?42. cyclone i/o standard output delay adders for fast slew rate on column pins (part 2 of 2) standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max
4?26 altera corporation preliminary january 2004 cyclone device handbook, volume 1 1.8-v lvttl 2 ma 2,283 2,625 2,968 ps 8 ma 997 1,146 1,296 ps 12 ma 785 902 1,020 ps 1.5-v lvttl 2 ma 3,281 3,773 4,265 ps 4 ma 1,601 1,841 2,081 ps 8 ma 1,285 1,477 1,670 ps 3.3-v pci (1) 116 133 150 ps sstl-3 class i 583 670 758 ps sstl-3 class ii 182 209 236 ps sstl-2 class i 508 584 660 ps sstl-2 class ii 235 270 305 ps lv d s ? 5 ? 6 ? 7ps table 4?44. cyclone i/o standard output delay adders for slow slew rate on column pins (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max lvcmos 2 ma 2,793 3,212 3,631 ps 4 ma 2,304 2,649 2,995 ps 8 ma 1,938 2,228 2,519 ps 12 ma 1,800 2,070 2,340 ps 3.3-v lvttl 4 ma 2,824 3,247 3,671 ps 8 ma 2,477 2,847 3,219 ps 12 ma 1,966 2,260 2,555 ps 16 ma 2,005 2,305 2,606 ps 24 ma 1,831 2,105 2,380 ps 2.5-v lvttl 2 ma 3,740 4,300 4,861 ps 8 ma 2,750 3,161 3,574 ps 12 ma 2,756 3,168 3,582 ps 16 ma 2,616 3,007 3,400 ps 1.8-v lvttl 2 ma 6,499 7,473 8,448 ps 8 ma 5,213 5,994 6,776 ps 12 ma 5,001 5,750 6,500 ps table 4?43. cyclone i/o standard output delay adders for fast slew rate on row pins (part 2 of 2) standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max
altera corporation 4?27 january 2004 preliminary timing model 1.5-v lvttl 2 ma 7,782 8,949 10,116 ps 4 ma 6,102 7,017 7,932 ps 8 ma 5,786 6,653 7,521 ps sstl-3 class i 2,383 2,740 3,098 ps sstl-3 class ii 1,982 2,279 2,576 ps sstl-2 class i 2,958 3,401 3,845 ps sstl-2 class ii 2,685 3,087 3,490 ps lvds 1,795 2,064 2,333 ps table 4?45. cyclone i/o standard output delay adders for slow slew rate on row pins (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max lvcmos 2 ma 2,793 3,212 3,631 ps 4 ma 2,304 2,649 2,995 ps 8 ma 1,938 2,228 2,519 ps 12 ma 1,800 2,070 2,340 ps 3.3-v lvttl 4 ma 2,824 3,247 3,671 ps 8 ma 2,477 2,847 3,219 ps 12 ma 1,966 2,260 2,555 ps 16 ma 2,005 2,305 2,606 ps 24 ma 1,831 2,105 2,380 ps 2.5-v lvttl 2 ma 3,740 4,300 4,861 ps 8 ma 2,750 3,161 3,574 ps 12 ma 2,756 3,168 3,582 ps 16 ma 2,616 3,007 3,400 ps 1.8-v lvttl 2 ma 6,499 7,473 8,448 ps 8 ma 5,213 5,994 6,776 ps 12 ma 5,001 5,750 6,500 ps 1.5-v lvttl 2 ma 7,782 8,949 10,116 ps 4 ma 6,102 7,017 7,932 ps 8 ma 5,786 6,653 7,521 ps 3.3-v pci 1,916 2,203 2,490 ps table 4?44. cyclone i/o standard output delay adders for slow slew rate on column pins (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max
4?28 altera corporation preliminary january 2004 cyclone device handbook, volume 1 tables 4?46 through 4?47 show the adder delays for the ioe programmable delays. these delays are controlled with the quartus ii software options listed in the parameter column. sstl-3 class i 2,383 2,740 3,098 ps sstl-3 class ii 1,982 2,279 2,576 ps sstl-2 class i 2,958 3,401 3,845 ps sstl-2 class ii 2,685 3,087 3,490 ps lvds 1,795 2,064 2,333 ps note to tables 4?40 through 4?45 : (1) ep1c3 devices do not support the pci i/o standard. table 4?45. cyclone i/o standard output delay adders for slow slew rate on row pins (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max table 4?46. cyclone ioe programmable delays on column pins parameter setting -6 speed grade -7 speed grade -8 speed grade unit min max min max min max decrease input delay to internal cells off 3,057 3,515 3,974 ps small 2,639 3,034 3,430 ps medium 2,212 2,543 2,875 ps large 155 178 201 ps on 155 178 201 ps decrease input delay to input register off 3,057 3,515 3,974 ps on 000ps increase delay to output pin off 000ps on 552 634 717 ps
altera corporation 4?29 january 2004 preliminary timing model maximum input & output clock rates tables 4?48 and 4?49 show the maximum input clock rate for column and row pins in cyclone devices. table 4?47. cyclone ioe programmable delays on row pins parameter setting -6 speed grade -7 speed grade -8 speed grade unit min max min max min max decrease input delay to internal cells off 3,057 3,515 3,974 ps small 2,639 3,034 3,430 ps medium 2,212 2,543 2,875 ps large 154 177 200 ps on 154 177 200 ps decrease input delay to input register off 3,057 3,515 3,974 ps on 000ps increase delay to output pin off 000ps on 556 639 722 ps table 4?48. cyclone maximum input clock rate for column pins i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 464 428 387 mhz 2.5 v 392 302 207 mhz 1.8 v 387 311 252 mhz 1.5 v 387 320 243 mhz lvcmos 405 374 333 mhz sstl-3 class i 405 356 293 mhz sstl-3 class ii 414 365 302 mhz sstl-2 class i 464 428 396 mhz sstl-2 class ii 473 432 396 mhz lvds 567 549 531 mhz
4?30 altera corporation preliminary january 2004 cyclone device handbook, volume 1 tables 4?50 and 4?51 show the maximum output clock rate for column and row pins in cyclone devices. table 4?49. cyclone maximum input clock rate for row pins i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 464 428 387 mhz 2.5 v 392 302 207 mhz 1.8 v 387 311 252 mhz 1.5 v 387 320 243 mhz lvcmos 405 374 333 mhz sstl-3 class i 405 356 293 mhz sstl-3 class ii 414 365 302 mhz sstl-2 class i 464 428 396 mhz sstl-2 class ii 473 432 396 mhz 3.3-v pci (1) 464 428 387 mhz lvds 567 549 531 mhz note to tables 4?48 through 4?49 : (1) ep1c3 devices do not support the pci i/o standard. these parameters are only available on row i/o pins. table 4?50. cyclone maximum output clock rate for column pins i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 296 285 273 mhz 2.5 v 381 366 349 mhz 1.8 v 286 277 267 mhz 1.5 v 219 208 195 mhz lvcmos 367 356 343 mhz sstl-3 class i 169 166 162 mhz sstl-3 class ii 160 151 146 mhz sstl-2 class i 160 151 142 mhz sstl-2 class ii 131 123 115 mhz lvds 328 303 275 mhz
altera corporation 4?31 january 2004 preliminary timing model pll timing table 4?52 describes the cyclone fpga pll specifications. table 4?51. cyclone maximum output clock rate for row pins i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 296 285 273 mhz 2.5 v 381 366 349 mhz 1.8 v 286 277 267 mhz 1.5 v 219 208 195 mhz lvcmos 367 356 343 mhz sstl-3 class i 169 166 162 mhz sstl-3 class ii 160 151 146 mhz sstl-2 class i 160 151 142 mhz sstl-2 class ii 131 123 115 mhz 3.3-v pci (1) 66 66 66 mhz lvds 328 303 275 mhz note to tables 4?50 thorugh 4?51 : (1) ep1c3 devices do not support the pci i/o standard. these parameters are only available on row i/o pins. table 4?52. cyclone pll specifications note (1) (part 1 of 2) symbol parameter min max unit f in input frequency (-6 speed grade) 15.625 464 mhz input frequency (-7 speed grade) 15.625 428 mhz input frequency (-8 speed grade) 15.625 387 mhz f in duty input clock duty cycle 40.00 60 % t in jitter input clock period jitter 200 ps f out_ext (external pll clock output) pll output frequency (-6 speed grade) 15.625 320 mhz pll output frequency (-7 speed grade) 15.625 320 mhz pll output frequency (-8 speed grade) 15.625 275 mhz
4?32 altera corporation preliminary january 2004 cyclone device handbook, volume 1 f out (to global clock) pll output frequency (-6 speed grade) 15.625 405 mhz pll output frequency (-7 speed grade) 15.625 320 mhz pll output frequency (-8 speed grade) 15.625 275 mhz t out duty duty cycle for external clock output (when set to 50 % ) 45.00 55 % t jitter (2) period jitter for external clock output 300 (3) ps t lock (4) time required to lock from end of device configuration 10.00 100 s f vco pll internal vco operating range 500.00 1,000 mhz m counter values 2 to 32 integer n, g0, g1, e counter values 1 32 integer notes to table 4?52 : (1) these numbers are preliminary and pending silicon characterization. (2) the t jitter specification for the pll[2..1]_out pins are dependent on the i/o pins in its v ccio bank, how many of them are switching outputs, how much they toggle, an d whether or not they use programmable current strength or slow slew rate. (3) f out 100 mhz. when the pll external clock output frequency (f out ) is smaller than 100 mhz, the jitter specification is 60 mui. (4) f in/n must be greater than 200 mhz to ensure correct lock circuit operation below ?20 c. table 4?52. cyclone pll specifications note (1) (part 2 of 2) symbol parameter min max unit
altera corporation 5?1 may 2003 preliminary 5. reference & ordering information software cyclone devices are supported by the altera quartus ? ii design software, which provides a comprehensiv e environment for system-on-a- programmable-chip (sopc) design. the quartus ii software includes hdl and schematic design entry, comp ilation and logic synthesis, full simulation and advanced timing analys is, signaltap ii logic analysis, and device configuration. see the design software selector guide for more details on the quartus ii software features. the quartus ii software supports the windows 2000/nt/98, sun solaris, linux red hat v7.1 and hp-ux operating systems. it also supports seamless integration with industry-leading eda tools through the nativelink ? interface. device pin-outs device pin-outs for cyclone devices are available on the altera web site ( www.altera.com ) and in the cyclone fpga device handbook . ordering information figure 5?1 describes the ordering codes for cyclone devices. for more information on a specific package, refer to chapter 6, package information for cyclone devices . figure 5?1. cyclone device packaging ordering information device type package type 6, 7, or 8 , with 6 being the fastest number of pins for a particular package es: t: q: f: thin quad flat pack (tqfp) plastic quad flat pack (pqfp) fineline bga ep1c: cyclone 3 4 6 12 20 c: i: commercial temperature (t j = 0 ? c to 85 ? c) industrial temperature (t j = -40 ? c to 100 ? c) optional suffix family signature operating temperature speed grade pin count engineering sample 7 ep1c 20 c 400 fes indicates specific device options or shipment method. c51005-1.0
5?2 altera corporation preliminary may 2003 cyclone device handbook, volume 1
altera corporation 12?17 july 2003 preliminary voltage regulators figure 12?15. el7556bc: 5.0-v-to-1.5-v/6-a synchronous switching regulator notes to figures 12?13 ? 12?15 : (1) these capacitors are ceramic capacitors. (2) these capacitors are ceramic or tantalum capacitor. (3) these are bat54s fast diodes. (4) d4 is only required for el7556acm. (5) this is a sprague 293d337x96r3 2x330 f capacitor. (6) this is a sprague 293d337x96r3 3x330 f capacitor. c 11 (2) 0.22 f c 10 (6) 1.0 mf c 5 (2) 1 f c 4 (1) 0.1 f c 6 (1) 0.1 f c 8 (1) 220 pf c 7 (1) 39 pf c 12 1.0 f c 9 (5) 660 f v in test pwrgd ot fb1 outen c slope v dd v ssp v ssp v ssp v ssp v ssp v cc2det v in v in c ref c osc fb2 c 2v v hi lx lx v ssp v ssp lx lx c p v ss el7556bc r 5 5.1 ? r 4 100 ? l 1 2.5 h r 6 39.2 ? r 1 20 ? d 4 optional (3), (4) v out = 1.5 v (1 + ) r 3 50 ? v in d 3 (3) d 2 (3) d 1 (3) r 3 r 4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14
12?18 altera corporation preliminary july 2003 cyclone device handbook, volume 1 figures 12?16 and 12?17 show the switching regulator that converts 3.3 v to 1.5 v with different output currents. figure 12?16. el7562cm: 3.3-v to 1.5-v/2-a synchronous switching regulator figure 12?17. el7563cm: 3.3-v to 1.5-v/4-a synchronous switching regulator v out 1.5 v 2 a v in 3.3 v sgnd v dd pgnd v in v in en c osc pgnd pgnd fb lx v hi lx pgnd v ref v drv el7562cm 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 r 3 39 ? c 5 0.1 f c 6 0.1 f c 8 0.1 f c 2 0.1 f c 3 0.1 f c 4 270 pf c 1 100 f c 9 0.1 f c 7 100 f l 1 2.5 h r 2 539 ? r 1 1 k ? d 2 d 3 d 4 v out 1.5 v 4 a v in 3.3 v v ref c osc v tj pgnd pgnd v in sgnd v dd en pg v hi lx lx pgnd fb v drv el7563cm 20 19 18 17 16 15 14 13 pgnd pgnd stp stn 12 11 9 10 1 2 3 4 5 6 7 8 r 4 22 ? c 7 330 f l 1 2.5 h r 2 513 ? r 1 1 k ? c 3 0.22 f c 6 0.22 f c 10 2.2 nf c 1 330 f c 9 0.1 f c 8 0.22 f c 2 2.2 nf c 4 390 pf c 5 0.1 f d 1 d 3 d 2 d 4
altera corporation 12?19 july 2003 preliminary 1.5-v regulator application examples 1.5-v regulator application examples the following sections show the process used to select a voltage regulator for three sample designs. the regulato r selection is based on the amount of power that the cyclone device co nsumes. there are 14 variables to consider when selecting a voltage regulator. the following variables apply to cyclone devi ce power consumption: f max output and bidirectional pins average toggle rate for i/o pins (tog io ) average toggle rate for logic elements (les) (tog lc ) user-mode i cc consumption maximum power-up i ccint requirement utilization v ccio supply level v ccint supply level the following variables apply to the voltage regulator: output voltage precision requirement supply voltage on the board voltage supply output current variance of board supply efficiency different designs have different power consumptions based on the variables listed. once you calculate the cyclone device?s power consumption, you must consider ho w much current the cyclone device needs. you can use the cyclone power calculator (available at www.altera.com ) or the powergauge tm tool in the quartus ii software to determine the current needs. also check the maximum power-up current requirement listed in the power co nsumption section of the cyclone fpga family data sheet because the power-up current requirement may exceed the user-mode current consumption for a specific design. once you determine the minimum curre nt the cyclone device requires, you must select a voltage regulator th at can generate the desired output current with the voltage and current su pply that is available on the board using the variables listed in this section. an example is shown to illustrate the voltage regulator selection process.
12?20 altera corporation preliminary july 2003 cyclone device handbook, volume 1 synchronous switching regulator example this example shows a worst-case sc enario for power consumption where the design uses all the les and ram. table 12?7 shows the design requirements for 1.5-v design using a cyclone ep1c12 fpga. table 12?8 uses the checklist on page 12?8 to help select the appropriate voltage regulator. table 12?7. design requirements for the example ep1c12f324c design requirement value output voltage precision requirement 5 % supply voltages available on the board 3.3 v voltage supply output current available for this section (i in, dc(max) ) 2 a variance of board supply (v in ) 5 % f max 150 mhz average tog io 12.5 % average tog lc 12.5 % utilization 100 % output and bidirectional pins 125 v ccio supply level 3.3 v v ccint supply level 1.5 v efficiency 90 % table 12?8. voltage regulator selection process for ep1c12f324c design (part 1 of 2) output voltage requirements v out = 1.5 v supply voltages v in or v cc = 3.3 v supply variance from linear technol ogy data sheet supply variance = 5 % estimated i ccint use cyclone power calculator i ccint = 620 ma estimated i ccio if regulator powers v ccio use cyclone power calculator (not applicable in this example because v ccio = 3.3 v) i ccio = n/a total user-mode current consumption i cc = i ccint + i ccio i cc = 620 ma
altera corporation 12?21 july 2003 preliminary board layout board layout laying out a printed circuit board (p cb) properly is extremely important in high-frequency ( 100 khz) switching regulator designs. a poor pcb layout results in increased emi and ground bounce, which affects the reliability of the voltage regulator by obscuring important voltage and current feedback signals. altera recommends using gerber files ? pre- designed layout files ? supplied by the regulator vendor for your board layout. if you cannot use the supplied layout files, contact the voltage regulator vendor for help on re-designing the bo ard to fit your design requirements while maintaining the proper functionality. altera recommends that you use separa te layers for sign als, the ground plane, and voltage supply planes. yo u can support separate layers by using multi-layer pcbs, assuming you are using two signal layers. ep1c12 maximum power-up current requirement see power consumption section of the cyclone fpga family data sheet for other densities i puc(max) = 900 ma maximum output current required compare i cc with i puc(max) i out(max) = 900 ma voltage regulator selection see linear technology ltc 1649 data sheet see intersil (elantec) el7562c data sheet ltc1649 i out(max) = el7562c i out(max) = 15 a 2 a ltc1649 nominal efficiency ( ) nominal efficiency ( ) = > 90 % line and load regulation line regulation + load regulation = (0.17 mv + 7 mv)/ 1.5 v 100 % line and load regulation = 0.478 % < 5 % minimum input voltage (v in(min) ) (v in(min) ) = v in (1 ? ? v in ) = 3.3v(1 ? 0.05) (v in(min) ) = 3.135 v maximum input current i in, dc(max) = (v out i out(max) )/( v in(min) ) i in, dc(max) = 478 ma < 2 a el7562c nominal efficiency ( ) nominal efficiency ( ) = > 95 % line and load regulation line regulation + load regulation = (0.17 mv + 7 mv)/ 1.5 v 100 % line and load regulation = 0.5 % < 5 % minimum input voltage (v in(min) ) (v in(min) ) = v in (1 ? ? v in ) = 3.3v(1 ? 0.05) (v in(min) ) = 3.135 v maximum input current i in, dc(max) = (v out i out(max) )/( v in(min) ) i in, dc(max) = 453 ma < 2 a table 12?8. voltage regulator selection process for ep1c12f324c design (part 2 of 2)
12?22 altera corporation preliminary july 2003 cyclone device handbook, volume 1 figure 12?18 shows how to use regulators to generate 1.5-v and 2.5-v power supplies if the system needs two power supply systems. one regulator is used for each power supply. figure 12?18. two regulator solution for systems that require 5.0-v, 2.5-v & 1.5-v supply levels figure 12?19 shows how to use a single regulator to generate two different power supplies (1.5-v and 2.5-v ). the use of a single regulator to generate 1.5-v and 2.5-v supplie s from the 5.0-v power supply can minimize the board size and thus save cost. figure 12?19. single regulator solution for systems that require 5.0-v, 2.5-v & 1.5-v supply levels regulator regulator 2.5-v device 1.5-v device altera cyclone fpga 1.5 v 5.0 v 2.5 v pcb regulator 2.5-v device 1.5-v device altera cyclone fpga 1.5 v 5.0 v 2.5 v pcb
altera corporation 12?23 july 2003 preliminary conclusion split-plane method the split-plane design method reduces the number of planes required by placing two power supply pl anes in one plane (see figure 12?20 ). for example, the layout for this method can be structured as follows: one 2.5-v plane, covering the entire board one plane split between 5.0-v and 1.5-v this technique assumes that the majority of devices are 2.5-v. to support multivolt i/o, altera devices must have access to 1.5-v and 2.5-v planes. figure 12?20. split board layout for 2.5-v systems with 5.0-v & 1.5-v devices conclusion with the proliferation of multiple voltage levels in systems, it is important to design a voltage syst em that can support a low-power device like cyclone devices. designers must consider key elements of the pcb, such as power supplies, regula tors, power consumption, and board layout when successfully designing a system that incorporates the low- voltage cyclone family of devices. 2.5-v device 2.5-v device 2.5-v device 5.0-v device 5.0-v device 1.5-v device 1.5-v device 2.5-v device altera cyclone fpga (1.5 v) 1.5 v pcb 5.0 v regulator
12?24 altera corporation preliminary july 2003 cyclone device handbook, volume 1 references linear technology corporation. application note 35 (step-down switching regulators) . milpitas: linear techno logy corporation, 1989. linear technology corporation. lt1573 data sheet (low dropout regulator driver) . milpitas: linear techno logy corporation, 1997. linear technology corporation. lt1083/lt1084/lt1085 data sheet (7.5 a, 5 a, 3 a low dropout positi ve adjustable regulators) . milpitas: linear technology corporation, 1994. linear technology corporation. ltc1649 data sheet (3.3v input high power step-down switching regulator controller) . milpitas: linear technology corporation, 1998. linear technology corporation. ltc1775 data sheet (high power no rsense current mode synchronous step-down switching regulator) . milpitas: linear techno logy corporation, 1999. intersil corporation. el7551c data sheet (monolithic 1 amp dc:dc step- down regulator) . milpitas: intersil corporation, 2002. intersil corporation. el7564c data sheet (monolithic 4 amp dc:dc step- down regulator) . milpitas: intersil corporation, 2002. intersil corporation. el7556bc data sheet (integrated adjustable 6 amp synchronous switcher) . milpitas: intersil corporation, 2001. intersil corporation. el7562c data sheet (monolithic 2 amp dc:dc step- down regulator) . milpitas: intersil corporation, 2002. intersil corporation. el7563c data sheet (monolithic 4 amp dc:dc step- down regulator) . milpitas: intersil corporation, 2002.
altera corporation section vi?1 preliminary section vi. configuration this section provides information for all of the supported configuration schemes for cyclone devices. the last chapter provides information on epcs1 and epcs4 serial configuration devices. this section contains the following chapters: chapter 13. configuring cyclone fpgas chapter 14. serial configuratio n devices (epcs1 & epcs4) data sheet revision history the table below shows the revision history for chapter 13 and 14 . chapter(s) date / version changes made 13 july 2003 v1.1 updated .rbf sizes. minor updates throughout the document. may 2003 v1.0 added document to cyclone device handbook. 14 october 2003 v1.2 added serial configuration device memory access section. updated timing information in tables 14?10 and 14?11 . july 2003 v1.1 minor updates. may 2003 v1.0 added document to cyclone device handbook.
section vi?2 altera corporation preliminary configuration cyclone device handbook, volume 1
altera corporation 13?1 july 2003 preliminary 13. configuring cyclone fpgas introduction you can configure cyclone tm fpgas using one of several configuration schemes, including the new active seri al (as) configurat ion scheme. this new scheme is used with the new, lo w cost serial configuration devices. passive serial (ps) and joint te st action group (jtag)-based configuration schemes are also supported by cyclone fpgas. additionally, cyclone fpgas can receive a compressed configuration bit stream and decompress this data in real-time, reducing storage requirements and configuration time. this chapter describes how to configure cyclone devices using each of the three supported configuration schemes. device configuration overview cyclone fpgas use sram cells to store configuration data. since sram memory is volatile, configuration data must be downloaded to cyclone fpgas each time the device powers up. you can download configuration data to cyclone fpgas using the as, ps, or jtag interfaces. see table 13?1 . you can select a cyclone fpga configuration scheme by driving its msel1 and msel0 pins either high ( 1 ) or low ( 0 ), as shown in table 13?2 . if your application only requires a single configuration mode, the msel table 13?1. cyclone fpga configuration schemes configuration scheme description active serial (as) confi guration configuration using: serial configuration devices (epcs1 or epcs4) passive serial (ps) configuration configuration using: enhanced configuration devices (epc4, epc8, and epc16) epc2, epc1 configuration devices intelligent host (microprocessor) download cable jtag-based configuration configu ration via jtag pins using: download cable intelligent host (microprocessor) jam tm standard test and programming language (stapl) c51013-1.1
13?2 altera corporation preliminary july 2003 cyclone device handbook, volume 1 pins can be connected to v cc (the i/o bank?s v ccio voltage where the msel pin resides) or to ground. if your application requires more than one configuration mode, the msel pins can be switched after the fpga has been configured successfully. togg ling these pins during user mode will not affect the device operation. however, the msel pins must be valid before initiating reconfiguration. after configuration, cyclone fpgas will initialize registers and i/o pins, then enter user mode and function as per the user design. figure 13?1 shows an as configuration waveform. figure 13?1. as configuration waveform table 13?2. selecting cyclone configuration schemes msel1 msel0 configuration scheme 00 as 01 ps 0 0 or 1 (1) jtag-based (2) notes to ta b l e 1 3 ? 2 : (1) do not leave msel pins floating. connect them to a low- or high-logic level. these pins support the non-jtag configuration scheme used in production. if your design only uses jtag configuration, you should connect the msel0 pin to v cc . (2) jtag-based configuration takes preced ence over other schemes, which means that msel pin settings are ignored. read address bit n ? 1 bit n bit 1 bit 0 136 cycles nstatus nconfig conf_done ncso dclk asdo data0 init_done user i/o user mode
altera corporation 13?3 july 2003 preliminary data compression you can configure cyclone fpgas using the 3.3-v, 2.5-v, 1.8-v, or 1.5-v lvttl i/o standard on configuration and jtag input pins. these devices do not feature a vccsel pin; therefore, you should connect the vccio pins of the i/o banks containi ng configuration or jtag pins according to the i/o standard specifications. table 13?3 summarizes the approximate uncompressed configuration file size for each cyclone fpga. to calc ulate the amount of storage space required for multi-device configurations, add the file size of each device together. you should only use the numbers in table 13?3 to estimate the configuration file size before design compilation. different file formats, such as .hex or .ttf files, will have different file sizes. for any specific version of the quartus ? ii software, any design targeted for the same device has the same uncompressed configuration file size. if compression is used, the file size can vary after each compilation. data compression cyclone fpgas are the first fpgas to support decompression of configuration data. this feature allows you to store compressed configuration data in configuration devices or other memory, and transmit this compressed bit stream to cyclone fpgas. during configuration, the cyclone fpga decomp resses the bit stream in real time and programs its sram cells. cyclone fpgas support compression in the as and ps configuration schemes. compression is not supported for jtag-based configuration. 1 preliminary data indicates that compression reduces configuration bit stream size by 35 to 60 % . table 13?3. cyclone raw binary file (.rbf) sizes note (1) device data size (bit s) data size (bytes) ep1c3 627,376 78,422 ep1c4 925,000 115,625 ep1c6 1,167,216 145,902 ep1c12 2,326,528 290,816 ep1c20 3,559,608 444,951 note to table 13?3 : (1) these values are preliminary.
13?4 altera corporation preliminary july 2003 cyclone device handbook, volume 1 when you enable compression, the quartus ii software generates configuration files with compressed configuration data. this compression reduces the storage requirements in the configuration device or flash, and decreases the time needed to transmit the bit stream to the cyclone fpga. there are two methods to enable co mpression for cyclone bitstreams: before design compilation (in the compiler settings menu) and after design compilation (in the conv ert programming files window). to enable compression in the project's compiler settings, select device under the assignments menu to br ing up the settings window. after selecting your cyclone device open the device & pin options window, and in the general settings tab enable the check box for generate compressed bitstreams (as shown in figure 13?2 ). figure 13?2. enabling compression for cyclone bitstreams in compiler settings compression can also be enabled when creating programming files from the convert programming files window. see figure 13?3 . 1. click convert programming files (file menu).
altera corporation 13?5 july 2003 preliminary data compression 2. select the programming file type (pof, sram hexout, rbf, or ttf). 3. for pof output files, select a configuration device. 4. select add file and add a cyclone sof file(s). 5. select the name of the file you added to the sof data area and click on properties . 6. check the compression checkbox. figure 13?3. enabling compression for cy clone bitstreams in convert programming files when multiple cyclone devices are cascaded, the compression feature can be selectively enabled for each device in the chain. figure 13?4 depicts a chain of two cyclone fpgas. the first cyclone fpga has compression enabled and therefore receives a compressed bit stream from the configuration device. the second cyclone fpga has the compression feature disabled an d receives uncompressed data.
13?6 altera corporation preliminary july 2003 cyclone device handbook, volume 1 figure 13?4. compressed & uncompressed configuration data in the same programming file note (1) note to figure 13?4 : (1) the first device in the chain should be set up in as configuration mode ( msel[1..0]="00" ). the remaining devices in the chain must be set up in ps configuration mode ( msel[1..0]="01" ). you can generate programming files for this setup from the convert programming files window (file menu) in the quartus ii software. the decompression feature supported by cyclone fpgas is separate from the decompression feature in enhanced configuration devices (epc16, epc8, and epc4). the data co mpression feature in the enhanced configuration devices allows them to store compressed data and decompress the bit stream before transmitting to the target devices. when using cyclone fpgas with enhanced configuration devices, altera recommends using compression on one of the devices, not both (preferably the cyclone fpga since transmitting compressed data reduces configuration time). configuration schemes this section describes the various configuration schemes you can use to configure cyclone fpgas. descriptions include an overview of the protocol, pin connectio ns, and timing information. the schemes discussed are: as configuration (serial configuration devices) ps configuration jtag-based configuration nce gnd nceo decompression controller cyclone fpga nce nceo n.c. decompression controller cyclone fpga serial or enhanced configuration device serial data compressed uncompressed
altera corporation 13?7 july 2003 preliminary configuration schemes active serial configuration (s erial configuration devices) in the as configuration scheme, cyclone fpgas are configured using the new serial configuration devices. these configuration devices are low cost devices with non-volatile memory that feature a simple four-pin interface and a small form factor . these features make serial configuration devices an ideal solution for configuring the low-cost cyclone fpgas. f for more information on serial configuration devices, see chapter 14, serial configuration devices (epcs1 & epcs4) data sheet . serial configuration devices prov ide a serial interface to access configuration data. during device configuration, cyclone fpgas read configuration data via the serial interface, decompress data if necessary, and configure their sram cells. this scheme is referred to as an as configuration scheme because the fpga controls the configuration interface. this scheme is in contrast to the ps configuration scheme where the configuration device controls the interface. serial configuration devices have a fo ur-pin interface: serial clock input ( dclk ), serial data output ( data ), as data input ( asdi ), and an active- low chip select ( ncs ). this four-pin interface connects to cyclone fpga pins, as shown in figure 13?5 .
13?8 altera corporation preliminary july 2003 cyclone device handbook, volume 1 figure 13?5. as configuration of a single cyclone fpga notes to figure 13?5 : (1) connect the pull-up re sistors to a 3.3-v supply. (2) cyclone fpgas use the asdo to asdi path to control the configuration device. connecting the msel[1..0] pins to 00 selects the as configuration scheme. the cyclone chip enable signal, nce , must also be connected to ground or driven low for successful configuration. during system power up, both the cyclone fpga and serial configuration device enter a power-on reset (por) period. as soon as the cyclone fpga enters por, it drives nstatus low to indicate it is busy and drives conf_done low to indicate that it has not been configured. after por, which typically lasts 100 ms, the cyclone fpga releases nstatus and enters configurat ion mode when this signal is pulled high by the external 10-k ? resistor. once the fpga successfully exits por, all user i/o pins are tri-stated. cyclone devices have weak pull-up resistors on the user i/o pins which are on before and during configuration. f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in chapter 4, dc & switching characteristics . data dclk ncs asdi data0 dclk ncso asdo serial configuration device cyclone fpga 10 k ? 10 k ? v cc 10 k ? v cc v cc gnd nceo nce nstatus nconfig conf_done (2) msel1 msel0 gnd n.c. (1) (1) (1)
altera corporation 13?9 july 2003 preliminary configuration schemes the serial clock ( dclk ) generated by the cyclone fpga controls the entire configuration cycle (see figure 13?1 on page 13?2 ) and this clock signal provides the timing for the se rial interface. cy clone fpgas use an internal oscillator to generate dclk . table 13?4 shows the active serial dclk output frequencies. the serial configuration device latches input/control signals on the rising edge of dclk and drives out configuration data on the falling edge. cyclone fpgas drive out control signals on the falling edge of dclk and latch configuration data on the rising edge of dclk . in configuration mode, the cyclone fpga enables the serial configuration device by driving its ncso output pin low that is connected to the chip select ( ncs ) pin of the configurat ion device. the cyclone fpga?s serial clock ( dclk ) and serial data output ( asdo ) pins are used to read configuration data. the configuration device provides data on its serial data output ( data ) pin that is connected to the data0 input on cyclone fpgas. after all configuration bits are received by the cyclone fpga, it releases the open-drain conf_done pin allowing the external 10-k ? resistor to pull this signal to a high level. initialization begins only after the conf_done line reaches a high level. you can select the clock used for initialization by using the user supplied start-up clock option in the quartus ii software. the quartus ii software uses the 10-mhz (typical) in ternal oscillator (separate from the as internal oscillator) by default to initialize the cyclone fpga. when you enable the user supplied start-up clock option, the software uses the clkusr pin as the initialization cl ock. supplying a clock on the clkusr pin will not affect the conf iguration process. after all configuration data is accepted and the conf_done signal goes high, cyclone devices require 136 clock cycles to initialize properly. an optional init_done pin is available. this pin signals the end of initialization and the start of user mode with a low-to-high transition. the enable init_done output option is available in the quartus ii software. if the init_done pin is used, it will be high due to an external 10-k ? pull-up resistor when nconfig is low and during the beginning of configuration. once the option bit to enable init_done is programmed into the device (during the first frame of configuration table 13?4. active serial dclk output frequency minimum typical maximum units 14 17 20 mhz
13?10 altera corporation preliminary july 2003 cyclone device handbook, volume 1 data), the init_done pin will go low. when initialization is complete, the init_done pin will be released and pulled high. this low-to-high transition signals that the fpga has entered user mode. in user mode, the user i/o pins will no lo nger have weak pull-ups and will function as assigned in your design. if an error occurs during configur ation, the cyclone fpga asserts the nstatus signal low indicating a data frame error, and the conf_done signal will stay low. with the auto-restart configuration on frame error option enabled in the quartus ii software, the cyclone fpga resets the configuration device by pulsing ncso , releases nstatus after a reset time-out period (about 30 s), and retries configuration. if this option is turned off, the system must monitor nstatus for errors and then pulse nconfig low for at least 40 s to restart configuration. after successful configuration, the conf_done signal is tri-stated by the target device and then pulled high by the pull-up resistor. all as configuration pins, data0 , dclk , ncso , and asdo , have weak internal pull-up resistors. these pu ll-up resistors are always active. when the cyclone fpga is in user mode, you can initiate reconfiguration by pulling the nconfig pin low. the nconfig pin should be low for at least 40 s. when nconfig is pulled low, the fpga also pulls nstatus and conf_done low and all i/o pins are tri-stated. once nconfig returns to a logic high level and nstatus is released by the cyclone fpga, reconfiguration begins. configuring multip le devices (cascading) you can configure multiple cyclone fpgas using a single serial configuration device. you can cascade multiple cyclone fpgas using the chip-enable ( nce ) and chip-enable-out ( nceo ) pins. the first device in the chain must have its nce pin connected to ground . you must connect its nceo pin to the nce pin of the next device in the chain. when the first device captures all of its configuration data from the bit stream, it drives the nceo pin low enabling the next device in the chain. you must leave the nceo pin of the last device unconnected. the nconfig , nstatus , conf_done , dclk , and data0 pins of each device in the chain are connected (see figure 13?6 ). this first cyclone fpga in the chai n is the configuration master and controls configuration of the enti re chain. you must connect its msel pins to select the as configuration scheme. the remaining cyclone fpgas are configuration slaves and you must connect their msel pins to select the ps configuration scheme. figure 13?6 shows the pin connections for this setup.
altera corporation 13?11 july 2003 preliminary configuration schemes figure 13?6. configuring multiple devices using a serial configuration device (as) note to figure 13?6 : (1) connect the pull-up resistors to a 3.3-v supply. as shown in figure 13?6 , the nstatus and conf_done pins on all target fpgas are connected together with external pull-up resistors. these pins are open-drain bidirectional pins on the fpgas. when the first device asserts nceo (after receiving all of its configuration data), it releases its conf_done pin. but the subsequent devices in the chain keep this shared conf_done line low until they have rece ived their configuration data. when all target fpgas in the chain ha ve received their configuration data and have released conf_done , the pull-up resistor drives a high level on this line and all devices simultaneously enter initialization mode. if an error occurs at any point during configuration, the nstatus line is driven low by the failing fpga. if you enable the auto restart configuration on frame error option, reconfiguration of the entire chain begins after a reset time-out period (a maximum of 40 s). if the option is turned off, see 1 while you can cascade cyclone fpgas, serial configuration devices cannot be cascaded or chained together. data dclk ncs asdi data0 dclk ncso asdo serial configuration device cyclone fpga master 10 k ? 10 k ? v cc v cc gnd nceo nce nstatus conf_done data0 dclk cyclone fpga slave nceo nce nstatus conf_done 10 k ? v cc nconfig nconfig msel1 msel0 gnd v cc n.c. msel1 msel0 gnd (1) (1) (1)
13?12 altera corporation preliminary july 2003 cyclone device handbook, volume 1 if the configuration bit stream size exceeds the capacity of a serial configuration device, you must select a larger configuration device and/or enable the compression feature. while configuring multiple devices, the size of the bit stream is the sum of the individual devices? configuration bit streams. configuring mult iple devices with the same data certain applications require the configuration of multiple cyclone devices with the same design through a configuration bit stream or sof file. in active serial chains, this ca n be implemented by storing two copies of the sof file in the serial config uration device. the first copy would configure the master cyclone device, and the second copy would configure all remaining slave devices concurrently. the setup is similar to figure 13?6 where the master is setup in as mode ( msel=00 ), and the slave devices are setup in ps mode ( msel=01 ). to configure four identical cyclone devices with the same sof file, you could setup the chain similar to the example shown in figure 13?6 , except connect the three slave devices fo r concurrent configuration. the nceo pin from the master device drives the nce input pins on all three slave devices, and the data and dclk pins connect in parallel to all four devices. during the first configuration cycle, the master device reads its configuration data from the serial configuration device while holding nceo high. after completing its config uration cycle, the master drives nce low and transmits the second copy of the configuration data to all three slave devices, configuring them simultaneously. estimating active serial configuration time active serial configuration time is dominated by the time it takes to transfer data from the serial config uration device to the cyclone fpga. this serial interface is clocked by the cyclone dclk output (generated from an internal oscillator). as listed in table 13?4 , the dclk minimum frequency is 14 mhz (71 ns). therefor e, the maximum configuration time estimate for an ep1c3 device (0.628 mbits of uncompressed data) is: (0.628 mbits 71 ns) = 47 ms. the typical configuration time is 33 ms. enabling compression reduces the amount of configuration data that is transmitted to the cyclone device, reducing configuration time. on average, compression reduces configuration time by 50%.
altera corporation 13?13 july 2003 preliminary configuration schemes programming serial configuration devices serial configuration devices are non-volatile, flash-memory-based devices. you can program these devices in-system using the byteblaster tm ii download cable. alternati vely, you can program them using the altera programming unit (apu) or supported third-party programmers. you can perform in-system programmin g of serial conf iguration devices via the as programming interface. during in-system programming, the download cable disables fpga access to the as interface by driving the nce pin high. cyclone fpgas are also held in reset by a low level on nconfig . after programming is complete, the download cable releases nce and nconfig , allowing the pull-down and pull-up resistor to drive gnd and vcc , respectively. figure 13?7 shows the download cable connections to the serial configuration device. f for more information on the byteblaster ii cable, see the byteblaster ii download cable data sheet .
13?14 altera corporation preliminary july 2003 cyclone device handbook, volume 1 figure 13?7. in-system programming of serial configuration devices notes to figure 13?7 : (1) connect these pull-up resistors to 3.3-v supply. (2) the nceo pin is left unconnected. (3) power up the byteblaster ii cable?s v cc with a 3.3-v supply. you can program serial configuratio n devices by using the quartus ii software with the apu and the a ppropriate configuration device programming adapter. all serial configuration devices are offered in an eight-pin small outline integrated circuit (soic) package and can be programmed using the plmsepc-8 adapter. in production environments, serial configuration devices can be programmed using multiple method s. altera programming hardware (apu) or other third-party progra mming hardware can be used to program blank serial configuration de vices before they are mounted onto pcbs. alternatively, you can use an on-board microprocessor to program the serial configuration device in-system using c-based software drivers provided by altera. data dclk ncs asdi data0 dclk ncso nce nconfig nstatus nceo conf_done asdo v cc v cc v cc v cc 10 k ? 10 k ? 10 k ? 10 k ? cyclone fpga serial confi g uration device p in 1 msel1 msel0 gnd b y teb l aser ii 1 0 - p in ma l e h eader ( 2 ) n.c. (1) (1) (1) ( 3 )
altera corporation 13?15 july 2003 preliminary configuration schemes f for more information on programming serial configuration devices, see the cyclone literature web page and the serial configuration devices (epcs1 & epcs4) data sheet . passive serial configuration cyclone fpgas also feature the ps co nfiguration scheme supported by all altera fpgas. in the ps scheme, an external host (configuration device, embedded processor, or host pc) cont rols configuration. configuration data is clocked into the target cyclone fpgas via the data0 pin at each rising edge of dclk . the configuration waveforms for this scheme are shown in figure 13?8 . figure 13?8. ps configuration cycle waveform notes to figure 13?8 : (1) during initial power up and configuration, conf_done is low. after configuration, conf_done goes high to indicate successful configuration. if the device is reconfigured, conf_done goes low after nconfig is driven low. (2) user i/o pins are tri-stated during configuration. cyclone fpgas also have a weak pull-up resistor on i/o pins during configuration. after initialization, the user i/o pi ns perform the function assigned in the user?s design. (3) when used, the optional init_done signal is high when nconfig is low before configuration and during the first 136 clock cycles of configuration. (4) in user mode, dclk should be driven high or low when using th e ps configuration scheme. when using the as configuration scheme, dclk is a cyclone output pin and sh ould not be driven externally. (5) in user mode, data0 should be driven high or low. ps configuration usin g configuration device in the ps configuration device scheme, nconfig is usually tied to v cc (when using epc16, epc8, epc4, or epc2 devices, you can connect nconfig to ninit_conf ). upon device power-up, the target cyclone fpga senses the low-to-high transition on nconfig and initiates configuration. the target device then drives the open-drain conf_done pin low, which in-turn drives the configuration device?s ncs pin low. when exiting por, both the target and configuration device release the open-drain nstatus pin (typically cyclon e por lasts 100 ms). high-z nconfig nstatus conf_done (1) dclk data user i/o pins (2) init_done (3) mode high-z d0 d1 d2 d3 d(n ? 1) dn configuration initialization user high-z user i/o configuration (4) (5)
13?16 altera corporation preliminary july 2003 cyclone device handbook, volume 1 before configuration begins, the configuration device goes through a por delay of up to 100 ms (maximum) to allow the power supply to stabilize. you must power the cyclone fpga befo re or during the por time of the enhanced configuration device. during por, th e configuration device drives its oe pin low. this low signal delays configuration because the oe pin is connected to the target device?s nstatus pin. when the target and configuration devices complete por, they both release the nstatus to oe line, which is then pulled high by a pull-up resistor. when configuring multiple devices, configuration does not begin until all devices release their oe or nstatus pins. when all devices are ready, the configuration device clocks out data and dclk to the target devices using an internal oscillator. after successful configuration, the cyclone fpga starts initialization using the 10-mhz internal oscillator as the reference clock. the conf_done pin is released by the target device and then pulled high by a pull-up resistor. when initializati on is complete, the target cyclone fpga enters user mode. if an error occurs during configurat ion, the target device drives its nstatus pin low, resetting itself internally and resetting the configuration device. if you turn on the auto-restart configuration on frame error option, the device reconfigures automatically if an error occurs. to set this option, select compiler settings (processing menu), and click on the chips & devices tab. select device & pin options , and click on the configuration tab. if the auto-restart configuration on frame error option is turned off, the external system (configuration device or microprocessor) must monitor nstatus for errors and then pulse nconfig low to restart configuration. the external system can pulse nconfig if it is under system control rather than tied to v cc . when configuration is complete, the target device releases conf_done , which disables the configuration device by driving ncs high. the configuration device drives dclk low before and after configuration. in addition, if the configuration devi ce sends all of its data and then detects that conf_done has not gone high, it recognizes that the target device has not configured successfully. (for conf_done to reach a high state, enhanced configuration devices wait for 64 dclk cycles after the last configuration bit. epc2 devices wait for 16 dclk cycles.) in this case, the configuration device pulses its oe pin low for a few microseconds, driving the target device?s nstatus pin low. if the auto-restart configuration on frame error option is set in the quartus ii software, the
altera corporation 13?17 july 2003 preliminary configuration schemes target device resets and then releases its nstatus pin after a reset time- out period. when nstatus returns high, the configuration device reconfigures the target device. you should not pull conf_done low to delay initialization. instead, use the quartus ii software?s user-supplied start-up clock option to synchronize the initialization of multip le devices that are not in the same configuration chain. devices in the same configuration chain initialize together since their conf_done pins are tied together. for more information on this option, see ?device options? on page 13?45 . conf_done goes high during th e first few clock cycles of initialization. hence when using the clkusr feature you would not see the conf_done signal high until you start clocking clkusr . however, the device does retain configuration data and waits for these initialization clocks to release conf_done and go into user mode. 1 when using internal pull-up resistors on configuration devices, power the supply voltage on the cyclone fpga i/o pins (v ccio ) to 3.3-v. epc2, epc4, epc8, and epc16 devices support 3.3-v operation but not 2.5-v oper ation. therefore, you must set the v ccio voltages for the banks wher e programming pins reside to 3.3 v. figure 13?9 shows how to configure one cyclone fpga with one configuration device.
13?18 altera corporation preliminary july 2003 cyclone device handbook, volume 1 figure 13?9. single device configuration circuit notes to figure 13?9 : (1) the pull-up resistor should be conn ected to the same supply voltage as the configuration device. this pull-up resistor is 10 k ? . the epc16, epc8, epc4, and epc2 devices? oe and ncs pins have internal, user-configurable pull-up resistors. if you use internal pull-up re sistors, do not use external pull-up resistors on these pins. (2) the ninit_conf pin is available on epc16, epc8, epc4, and epc2 devices and has an internal pull-up resistor that is always active. if ninit_conf is not used, nconfig must be pulled to v cc through a resistor. (3) the nceo pin is left unconnected for the last device in the chain. (4) connect msel0 to the v cc supply voltage of the i/ o bank it resides in. configuring multiple cyclone fpgas you can use a single configuration device to configure multiple cyclone fpgas. in this setup, the nceo pin of the first device is connected to the nce pin of the second device in the chain. if there are additional devices, connect the nce pin of the next device to the nceo pin of the previous device. you should leave the nceo pin on the last device in the chain unconnected. to configure properly, all of the target device conf_done and nstatus pins must be tied together. figure 13?10 shows an example of configuring multiple cyclone fpgas using a single configuration device. cyclone fpga dclk data oe ncs ninit_conf ( 2 ) msel0 msel1 dclk data0 nstatus conf_done nconfig v cc v cc gnd (1) (1) nce nceo n.c. ( 3 ) confi g uration device 10 k ? 10 k ? 10 k ? v cc v cc (1) gnd (4)
altera corporation 13?19 july 2003 preliminary configuration schemes figure 13?10. configuring multiple cyclone fpgas with a single configuration device notes to figure 13?10 : (1) the pull-up resistor should be connected to the same supply voltage as the configuration device. the epc16, epc8, epc4, and epc2 devices? oe and ncs pins have internal, user-configurable pull-up resistors. if you use internal pull-up resistors, do not use extern al pull-up resistors on these pins. (2) epc16, epc8, and epc4 configuration devices cannot be cascaded. (3) the nceo pin is left unconnected for the last device in the chain. (4) the ninit_conf pin is available on epc16, epc8, epc4, and epc2 devices. if ninit_conf is not used, nconfig must be pulled to v cc through a resistor. (5) the ninit_conf pin has an internal pull-up resistor that is always active in epc16, epc8, epc4, and epc2 devices. these devices do not need an ex ternal pull-up resistor on the ninit_conf pin. (6) connect msel0 to the v cc supply voltage of the i/ o bank it resides in. when performing multi-device ps co nfiguration, you must generate the configuration device programming file ( .sof ) from each project. then you must combine multiple .sof files using the quartus ii software through the convert programming files dialog box. f for more information on how to create programmer object files ( .pof ) for enhanced configur ation devices, see an 218: using enhanced configuration devices . for a description of the various configuration and programming files, see ?device configuration files? on page 13?53 . after the first cyclone fpga completes config uration during multi- device configuration, its nceo pin activates the second device?s nce pin, prompting the second device to begin configuration. because all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. confi g uration device ( 2 ) dclk data oe ncs ninit_conf (4), (5) dclk data0 nstatus conf_done nconfig v cc v cc gnd nce v cc dclk data0 nstatus conf_done nconfig gnd nce msel1 nceo ncasc (1) (1) (1) nceo (3) n.c. cyclone fpga 2 cyclone fpga 1 msel0 v cc gnd msel1 msel0 v cc 10 k ? 10 k ? 10 k ? ( 6 ) ( 6 )
13?20 altera corporation preliminary july 2003 cyclone device handbook, volume 1 in addition, all nstatus pins are tied together; therefore, if any device (including the configuration device) detects an error, configuration stops for the entire chain. also, if the co nfiguration device does not detect conf_done going high at the end of config uration, it resets the chain by pulsing its oe pin low for a few microseconds. for conf_done to reach a high state, enhanced config uration devices wait for 64 dclk cycles after the last configuration bit. epc2 devices wait for 16 dclk cycles. if the auto-restart configuration on frame error option is turned on in the quartus ii software, the cyclone fpga releases its nstatus pins after a reset time-out period (ab out 30 micro-seconds). when the nstatus pins are released and pulled high, the configuration device reconfigures the chain. if the auto-restart configura tion on frame error option is not turned on, the devices drive nstatus low until they are reset with a low pulse on nconfig . you can also cascade several epc2 configuration devices to configure multiple cyclone fpgas. when all data from the first configuration device is sent, it drives ncasc low, which in turn drives ncs on the subsequent epc2 device. because a configuration device requires less than one clock cycle to activate a subsequent configuration device, the data stream is uninterrupted. you cannot cascade epc16, epc8, and epc4 configuration devices. programming configuration devices enhanced configuration devices (epc4, epc8, and epc16 devices) and epc2 devices support in-system programming via jtag. you can program these configuration devices using the quartus ii software and a download cable (e.g., byteblaster ii, masterblaster tm , or byteblastermv tm cables). you can also program configuration devices using the quartus ii software, the apu, and the appr opriate configuration device programming adapter. table 13?5 shows which programming adapter to use with each configuration device. table 13?5. programming adapters (part 1 of 2) device package adapter epc16 88-pin ultra fineline bga ? 100-pin pqfp plmuepc-88 plmqepc-100 epc8 100-pin pqfp plmqepc-100 epc4 100-pin pqfp plmqepc-100
altera corporation 13?21 july 2003 preliminary configuration schemes ps configuration using a download cable using a download cable in ps configuration, an intelligent host (e.g., your pc) transfers data from a storage devi ce (e.g., your hard drive) to the cyclone fpga through a byteblaster ii, masterblaster, or byteblastermv cable. to initiate configuration in this scheme, the download cable generates a low-to-high transition on the nconfig pin. the programming hardware then sends th e configuration data one bit at a time on the device?s data0 pin. the data is clocked into the target device using dclk until the conf_done goes high. when using programming hardware for the cyclone fpga, turning on the auto-restart configura tion on frame error option does not affect the configuration cycle because the quartus ii software must restart configuration when an error occurs. figure 13?11 shows the ps configuration setup for the cyclone fpga using a byteblaster ii, masterblaster, or byteblastermv cable. epc2 20-pin j-lead 32-pin tqfp plmj1213 plmt1213 epc1 8-pin dip 20-pin j-lead plmj1213 plmj1213 table 13?5. programming adapters (part 2 of 2) device package adapter
13?22 altera corporation preliminary july 2003 cyclone device handbook, volume 1 figure 13?11. ps configuration circuit with byteblaste r ii, masterblaster, or byteblastermv cable notes to figure 13?11 : (1) you should connect the pull-u p resistor to the same supply voltage as the masterblaster ( vio pin) or byteblastermv cable. (2) power supply voltage: v cc = 3.3-v for the byteblaster ii, masterblaster, and byteblastermv cable. (3) pin 6 of the header is a v io reference voltage for the ma sterblaster output driver. v io should match the device?s v ccio . this pin is a no-connect pin for the byteblastermv header. (4) the pull-up resistors on data0 and dclk are only needed if the download ca ble is the only configuration scheme used on your board. this is to ensure that data0 and dclk are not left floating after co nfiguration. for example, if you are also using a configuration device, the pull-up resistors on data0 and dclk are not needed. (5) connect msel0 to the v cc supply voltage of the i/ o bank it resides in. you can use the download cable to configure multiple cyclone fpgas by connecting each device?s nceo pin to the subs equent device?s nce pin. all other configuration pins are conn ected to each device in the chain. because all conf_done pins are tied together, all devices in the chain initialize and enter user mode at the same time. in addition, because the nstatus pins are tied together, the entire chain halts configuration if any device detects an error. in this si tuation, the quartus ii software must restart configuration; the auto-restart configuration on frame error option does not affect the configuration cycle. figure 13?12 shows how to configure multiple cyclone fpgas with a byteblaster ii, masterblaster, or byteblastermv cable. b y teb l aster ii , masterb l aster, o r b y teb l asterm v 1 0 - p in ma l e h eader v cc (1) v cc (1) v cc ( 2 ) v cc (1) cyclone device dclk nconfig conf_done shield gnd msel1 msel0 10 k ? 10 k ? 10 k ? nstatus data0 p in 1 nce gnd gnd vio ( 3 ) v cc v cc (1) 10 k ? (4) v cc (1) 10 k ? (4) (5)
altera corporation 13?23 july 2003 preliminary configuration schemes figure 13?12. multi-device ps configuration with a byteblaster ii, masterblaster, or byteblastermv cable notes to figure 13?12 : (1) you should connect the pull-u p resistor to the same supply voltage as the masterblaster ( vio pin) or byteblastermv cable. (2) power supply voltage: v cc = 3.3-v for the byteblaster ii, masterblaster, and byteblastermv cable. (3) v io is a reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable data sheet for this value. (4) the nceo pin is left unconnected for the last device in the chain. (5) the pull-up resistors on data0 and dclk are only needed if the download ca ble is the only configuration scheme used on your board. this is to ensure that data0 and dclk are not left floating after co nfiguration. for example, if you are also using a configuration device, the pull-up resistors on data0 and dclk are not needed. (6) connect msel0 to the v cc supply voltage of the i/ o bank it resides in. if you are using a byteblaster ii, mast erblaster, or byteblastermv cable to configure device(s) on a board that al so is populated with configuration devices, you should electrically isolate the configuration devices from the target device(s) and cable. one way to isolate the configuration devices is to add logic, such as a multiplexer, that can select between the configuration devices and the cable. the multiplexer allows bidirectional transfers on the nstatus and conf_done signals. another option is to cyclone fpga 1 cyclone fpga 2 msel0 nce nconfig conf_done dclk nce nceo nconfig conf_done dclk nceo gnd ( pass iv e ser i a l m o de ) v cc (2) v cc (1) gnd v cc (1) v cc (1) nstatus nstatus data0 data0 msel1 msel0 msel1 10 k ? 10 k ? 10 k ? p in 1 b y teb l aster ii , masterb l aster, o r b y teb l asterm v 1 0 - p in ma l e h eader n.c. (4) vio (3) gnd v cc gnd v cc v cc (1) 10 k ? (5) (6) v cc (1) 10 k ? (5)
13?24 altera corporation preliminary july 2003 cyclone device handbook, volume 1 add switches to the five common signals ( conf_done , nstatus , dclk , nconfig , and data0 ) between the cable and the configuration devices. the last option is to remove the configuration devices from the board when configuring with the cable. figure 13?13 shows a combination of a configuration device and a byteblaster ii, masterblaster, or byteblastermv cable to configure a cyclone fpga. figure 13?13. configuring with a combined ps & configuration device scheme notes to figure 13?13 : (1) you should connect the pull-up resistor to the same supply volt age as the configuration device. (2) power supply voltage: v cc = 3.3-v for the byteblaster ii, masterblaster, and byteblastermv cable. (3) pin 6 of the header is a v io reference voltage for the ma sterblaster output driver. v io should match the target device?s v ccio . this is a no-connect pin for the byteblastermv header. (4) the nceo pin is left unconnected. (5) you should not attempt configurat ion with a byteblaster ii, masterblas ter, or byteblastermv cable while a configuration device is connected to a cyclone fpga. instead, you should either remove the configuration device from its socket when using the download cable or place a switch on the five common signals between the download cable and the configuration device. remove the byteblaster ii, masterblaster, or byteblastermv cable when configuring with a configuration device. (6) if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (7) the pull-up resistors on data0 and dclk are only needed if the download ca ble is the only configuration scheme used on your board. this is to ensure that data0 and dclk are not left floating after co nfiguration. for example, if you are also using a configuration device, the pull-up resistors on data0 and dclk are not needed. (8) connect msel0 to the v cc supply voltage of the i/ o bank it resides in. cyclone fpga msel0 nce nconfig conf_done dclk nceo gnd b y teb l aster ii , masterb l aster, o r b y teb l asterm v 1 0 - p in ma l e h eader ( pass iv e ser i a l m o de ) v cc (2) v cc v cc (1) v cc (1) nstatus data0 msel1 10 k ? 10 k ? 10 k ? p in 1 dclk data oe ncs ninit_conf (6) confi g uration device (5) (5) (5) (5) (5) gnd vio (3) n.c. (4) (1) gnd v cc v cc 10 k ? (1) (7) (8) v cc 10 k ? (1) (7)
altera corporation 13?25 july 2003 preliminary configuration schemes f for more information on how to use th e byteblaster ii, masterblaster, or byteblastermv cables, see the following documents: byteblaster ii parallel port download cable data sheet masterblaster serial/usb co mmunications cable data sheet byteblastermv parallel port download cable data sheet ps configuration fr om a microprocessor in ps configuration with a microprocessor, a microprocessor transfers data from a storage device to the target cyclone fpga. to initiate configuration in this scheme, the micr oprocessor must generate a low-to- high transition on the nconfig pin and the target device must release nstatus . the microprocessor then places the configuration data one bit at a time on the data0 pin of the cyclone fpga. the least significant bit (lsb) of each data byte must be presented first. data is clocked continuously into the target device using dclk until the conf_done signal goes high. the cyclone fpga starts initialization using the internal oscillator after all configuration data is transferred. the device?s conf_done pin goes high to show successful configuration and the start of initialization. driving dclk to the device after configuration does not affect device operation. since the ps configuration scheme is a synchronous scheme, the configuration clock speed must be below the specified maximum frequency to ensure successful configuration. maximum dclk frequency supported by cyclone fpgas is 100 mhz (see table 13?6 on page 13?27 ). no maximum dclk period (i.e., minimum dclk frequency) exists. you can pause configuration by halting dclk for an indefinite amount of time. if the target device detects an error during configuration, it drives its nstatus pin low to alert the microprocessor. the microprocessor can then pulse nconfig low to restart the configuration process. alternatively, if the auto-restart configuration on frame error option is turned on in the quartus ii software, the target device releases nstatus after a reset time-out period. after nstatus is released, the microprocessor can reconfigure the target device without needing to pulse nconfig low. the microprocessor can also monitor the conf_done and init_done pins to ensure successful configuration and initialization. if the microprocessor sends all data but conf_done and init_done has not gone high, it must reconfigure the target device. figure 13?14 shows the circuit for ps configuratio n with a microprocessor.
13?26 altera corporation preliminary july 2003 cyclone device handbook, volume 1 figure 13?14. ps configuration circuit with a microprocessor notes to figure 13?14 : (1) the nceo pin is left unconnected. (2) connect msel0 to the v cc supply voltage of the i/ o bank it resides in. configuring cyclone fpgas with the microblaster software the microblaster tm software driver allows you to configure altera fpgas, including cyclone fpgas, through the byteblaster ii or byteblastermv cable in ps mode. the microblaster software driver supports a raw binary file ( .rbf ) programming input file and is targeted for embedded ps configuration. the source code is developed for the windows nt operating system, although you can customize it to run on other operating systems. for more information on the microblaster software driver, see the configuring the microblaster passive serial software driver white paper and source files on the altera web site at www.altera.com . passive serial timing for successful configur ation using the ps sc heme, several timing parameters such as setup, hold, an d maximum clock frequency must be satisfied. the enhanced configuration and epc2 devices are designed to meet these interface timing specifications. if you use a microprocessor or another intelligent host to control the ps interface, ensure that you meet these timing requirements. microprocessor conf_done nstatus nce data0 nconfig cyclone device memory addr data0 gnd msel1 v cc v cc 10 k ? 10 k ? gnd dclk nceo n.c. (1) msel0 v cc (2 )
altera corporation 13?27 july 2003 preliminary configuration schemes figure 13?15 shows the ps timing waveform for cyclone fpgas. figure 13?15. ps timing waveform for cyclone fpgas notes to figure 13?15 : (1) upon power-up, the cyclone fpga holds nstatus low for about 100 ms. (2) upon power-up and before configuration, conf_done is low. (3) in user mode, dclk should be driven high or low when using th e ps configuration scheme. when using the as configuration scheme, dclk is a cyclone output pin and sh ould not be driven externally. (4) data should not be left floating after configuration. it should be driven high or low, whichever is more convenient. table 13?6 contains the ps timing in formation for cyclone fpgas. nconfig nstatus (1) conf_done (2) dclk (3) data user i/o init_done bit 0 bit 1 bit 2 bit 3 bit n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck high-z user mode (4) table 13?6. ps timing parameters for cyclone devices note (1) (part 1 of 2) symbol parameter min max units t cf2cd nconfig low to conf_done low 800 ns t cf2st0 nconfig low to nstatus low 800 ns t cf2st1 nconfig high to nstatus high 40 (4) s t cfg nconfig low pulse width (2) 40 s t status nstatus low pulse width 10 40 (4) s t cf2ck nconfig high to first rising edge on dclk 40 s t st2ck nstatus high to first rising edge on dclk 1s t dsu data setup time before rising edge on dclk 7ns t dh data hold time after rising edge on dclk 0ns
13?28 altera corporation preliminary july 2003 cyclone device handbook, volume 1 jtag-based configuration jtag has developed a specification for boundary-scan testing. this boundary-scan test (bst) architecture offers the capability to efficiently test components on printed circuit boar ds (pcbs) with tight lead spacing. the bst architecture can test pin conn ections without using physical test probes and capture functional data wh ile a device is operating normally. you can also use the jtag circuitry to shift configuration data into cyclone fpgas. the quartus ii so ftware automatically generates .sof files that can be used for jtag configuration. f for more information on jtag boundary-scan testing, see an 39: ieee 1149.1 (jtag) boundary-sca n testing in altera devices . a device operating in jtag mode uses four required pins, tdi , tdo , tms , and tck . cyclone fpgas do not support the optional trst pin. the three jtag input pins, tck , tdi , and tms , have weak internal pull-up resistors. all user i/o pins are tri-stated during jtag configuration. cyclone is designed such that jtag instructions have precedence over any device operating modes. so jtag configuration can take place without waiting for other configuration to complete (e.g., configuration with serial or enhanced configurat ion devices). if you attempt jtag configuration in cyclone fpgas duri ng non-jtag configuration, non- jtag configuration will be terminat ed and jtag configuration will be initiated. t ch dclk high time 4ns t cl dclk low time 4ns t clk dclk period 10 ns f max dclk maximum frequency 100 mhz t cd2um conf_done high to user mode (3) 620s notes to table 13?6 : (1) this information is preliminary. (2) this value applies only if the internal oscillator is selected as the clock source for device initialization. if the clock source is clkusr , multiply the clock period by 270 to obtain this value. clkusr must be running during this period to reset the device. (3) the minimum and maximum numbers apply only if the intern al oscillator is chosen as the clock source for device initialization. if the clock source is clkusr , multiply the clock period by 140 to obtain this value. (4) you can obtain this value if you do not delay configuration by extending the nstatus low-pulse width. table 13?6. ps timing parameters for cyclone devices note (1) (part 2 of 2) symbol parameter min max units
altera corporation 13?29 july 2003 preliminary configuration schemes table 13?7 shows each jtag pin?s function. jtag configuration using a download cable during jtag configuration, data is downloaded to the device on the board through a byteblaster ii, byteblastermv, or masterblaster download cable. configuring devices through a cable is similar to programming devices in-system. see figure 13?16 for pin connection information. table 13?7. jtag pin descriptions pin description function tdi test data input serial input pin for instructions as well as test and programming data. data is shifted in on the rising edge of tck . tdo test data output serial data output pin for instruct ions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. tms test mode select input pin that provides the contro l signal to determine the transitions of the test access port ( tap) controller state machine. tr ansitions within the state machine occur on the rising edge of tck . therefore, tms must be set up before the rising edge of tck . tms is evaluated on the rising edge of tck . tck test clock input the clock input to the bst circuitry. some operations occur at the rising edge, while others occur at the falling edge.
13?30 altera corporation preliminary july 2003 cyclone device handbook, volume 1 figure 13?16. jtag configuration of single cyclone fpga notes to figure 13?16 : (1) you should connect the pull-u p resistor to the same supply voltage as the download cable. (2) you should connect the nconfig , msel0 , and msel1 pins to support a non-jtag configuration scheme. if you only use jtag configuration, connect nconfig to v cc , and msel0 and msel1 to ground. pull data0 and dclk to high or low. (3) v io is a reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable data sheet for this value. to configure a single device in a jtag chain, the programming software places all other devices in bypass mode. in bypass mode, devices pass programming data from the tdi pin to the tdo pin through a single bypass register without being affected internally. this scheme enables the programming software to program or verify the target device. configuration data driven into the device appears on the tdo pin one clock cycle later. the quartus ii software verifies succ essful jtag configuration upon completion. the software checks the state of conf_done through the jtag port. if conf_done is not high, the quartus ii software indicates that configuration has failed. if conf_done is high, the software indicates that configuration was successful. after the configuration bit stream is transmitted serially via the jtag tdi port, the tck port is clocked an additi onal 134 cycles to perform device initialization. 1 if v ccio is tied to 3.3-v, both the i/o pins and the jtag tdo port drive at 3.3-v levels. nce msel0 msel1 nconfig conf_done v cc (1) gnd v cc gnd v cc ( 2 ) ( 2 ) ( 2 ) 10 k ? 10 k ? nstatus b y teb l aster ii , masterb l aster, o r b y teb l asterm v 1 0 - p in ma l e h eader (to p vi e w) tck tdo tms tdi gnd vio ( 3 ) cyclone device data0 dclk ( 2 ) ( 2 ) p in 1 v cc 10 k ? v cc 10 k ? 10 k ? gnd
altera corporation 13?31 july 2003 preliminary configuration schemes cyclone fpgas have dedicated jtag pins. not only can you perform jtag testing on cyclone fpgas before and after, but also during configuration. while other device fa milies do not support jtag testing during configuration, cyclone fpgas support the bypass , idcode , and sample instructions during configuration without interrupting configuration. all other jtag instruct ions may only be issued by first interrupting configuration and reprogramming i/o pins using the config_io instruction. the config_io instruction allows i/o buffers to be configured via the jtag port, and when issued, interrupts configuration. this instruction allows you to perform board-level testing prior to configuring the cyclone fpga or waiting for a configuration device to complete configuration. once configuration ha s been interrupted and jtag testing is complete, the part must be reconfigured via jtag ( pulse_config instruction) or by pulsing nconfig low. the chip-wide reset and output enab le pins on cyclone fpgas do not affect jtag boundary-scan or prog ramming operations. toggling these pins does not affect jtag operations (other than the usual boundary-scan operation). when designing a board for jtag co nfiguration of cyclone fpgas, you should consider the regu lar configuration pins. table 13?8 shows how you should connect these pins during jtag configuration. table 13?8. jtag termination of unused pins (part 1 of 2) signal description nce drive all cyclone devices in the chain low by connecting nce to ground, pulling it down via a resistor, or driving it low by some control circ uitry. for devices in a multi-device ps and as configuration chains, connect the nce pins to ground during jtag configuration or configure them via jtag in the same or der as the configuration chain. nceo for all cyclone devices in a chain, the nceo pin can be left floating or connected to the nce pin of the previous device. nstatus pulled to v cc through a 10-k ? resistor. when configuring multiple devices in the same jtag chain, pull up each nstatus pin to v cc individually. (1) conf_done pulled to v cc through a 10-k ? resistor. when configuring multiple devices in the same jtag chain, pull up each conf_done pin to v cc individually. (1) nconfig driven high by connecting to v cc , pulling up through a resistor, or driving it high by some control circuitry.
13?32 altera corporation preliminary july 2003 cyclone device handbook, volume 1 jtag configuration of multiple devices when programming a jtag device ch ain, one jtag-compatible header, such as the byteblaster ii header, is connected to several devices. the number of devices in the jtag chain is limited only by the drive capacity of the download cable. however, when four or more devices are connected in a jtag chain, altera recommends buffering the tck , tdi , and tms pins with an on-board buffer. jtag-chain device configuration is ideal when the system contains multiple devices, or when testing your system using jtag bst circuitry. figure 13?17 shows multi-device jtag configuration. msel0, msel1 do not leave these pins floating. these pins support whichever non-jtag configuration is used in production. if only jtag co nfiguration is used, you shoul d tie these pins to ground. dclk do not leave these pins floating. drive lo w or high, whichever is more convenient. data0 do not leave these pins floating. drive lo w or high, whichever is more convenient. note to table 13?8 : (1) nstatus going low in the middle of jtag configuration indicates that an error has occurred; conf_done going high at the end of jtag configuratio n indicates successful configuration. table 13?8. jtag termination of unused pins (part 2 of 2) signal description
altera corporation 13?33 july 2003 preliminary configuration schemes figure 13?17. multi-device jtag configuration notes to figure 13?17 : (1) cyclone, apex tm ii, apex 20k, mercury tm , acex ? 1k, and flex ? 10k devices can be placed within the same jtag chain for device programming and configuration. (2) for more information on all configuration pins connected in this mode, refer to table 13?7 on page 13?29 . (3) these pull-up/pull-down resistors are 10 k ? . (4) connect the nconfig , msel0 , and msel1 pins to support a non-jtag configuration scheme. if only jtag configuration is used, connect nconfig to v cc , and msel0 and msel1 to ground. pull data0 and dclk to either high or low. (5) v io is a reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable data sheet for this value. connect the nce pin to ground or drive it lo w during jtag configuration. in multi-device ps and as configuration chains, connect the first device's nce pin to ground and connect the nceo pin to the nce pin of the next device in the chain. the last device's nce input comes from the previous device, while its nceo pin is left floating. after the first device completes configuration in a multi-device configuration chain, it?s nceo pin drives low to activate the second device's nce pin, which prompts the second device to begin configuration. therefore, if these devices are also in a jtag chain, you should make sure the nce pins are connected to ground during jtag configuration or that the devices are configured via jtag in the same order as the configuration chain. as long as the devices are configured in the same order as the multi-device configuration chain, the nceo pin of the previous device will drive the nce pin of the next device low when it has successfully been configured. figure 13?18 shows the jtag configuration of a cyclone fpga with a microprocessor. tms tck byteblaser ii, masterblaster, or byteblastermv 10-pin male header tdi tdo vcc (3) v cc v cc pin 1 nstatus nconfig msel1 nce v cc conf_done v cc tms tck tdi tdo nconfig msel1 nce v cc conf_done v cc tms tck tdi tdo nconfig msel1 nce v cc conf_done v cc (3) (4) (4) msel0 (4) (4) (4) msel0 (4) (4) dclk dclk dclk (4) (4) (4) data0 data0 data0 (4) (4) (4) (4) msel0 (4) vio (5) cyclone fpga cyclone fpga cyclone fpga (3) nstatus nstatus 10 k ? 10 k ? 10 k ? 10 k ? 10 k ? 10 k ?
13?34 altera corporation preliminary july 2003 cyclone device handbook, volume 1 figure 13?18. jtag configuration of cyclone fpgas with a microprocessor notes to figure 13?18 : (1) connect the nconfig , msel1 , and msel0 pins to support a non-jtag configuration scheme. if your design only uses jtag configuration, connect the nconfig pin to v cc and the msel1 and msel0 pins to ground. (2) pull data0 and dclk to either high or low. connecting the jtag chain to the embedded processor there are two ways to connect the jtag chain to the embedded processor. the most straightforward method is to connect the embedded processor directly to the jtag chain. in this method, four of the processor pins are dedicated to the jtag interface, saving board space but reducing the number of available embedded processor pins. figure 13?19 illustrates the second method, which is to connect the jtag chain to an existing bus through an interface programmable logic device (pld). in this method, the jtag chain becomes an address on the existing bus. the processor then reads from or writes to the address representing the jtag chain. nconfig data0 dclk tdi tck tms microprocessor memory addr data tdo cyclone fpga nstatus conf_done v cc v cc 10 k ? 10 k ? (2) (1) (2) (1) (1) msel1 msel0
altera corporation 13?35 july 2003 preliminary configuration schemes figure 13?19. embedded system block diagram notes to figure 13?19 : (1) connect the nconfig , msel1 , and msel0 pins to support a non-jtag configuration scheme. if your design only uses jtag configuration, connect the nconfig pin to v cc and the msel1 and msel0 pins to ground. (2) pull data0 and dclk to either high or low. configuring cyclone fpgas with jrunner jrunner is a software driver that allo ws you to configure altera fpgas, including cyclone fpgas, through the byteblaster ii or byteblastermv cables in jtag mode. the programmi ng input file supported is in .rbf format. jrunner also requires a chain description file ( .cdf ) generated by the quartus ii software. jrunner is targeted for embedded jtag configuration. the source code has been developed for the windows nt operating system (os). you can custom ize the code to make it run on tdi tms tck tdo tdi tms tck tdo tdi tms tck tdo tdi tms tck tdo tdi tms tck tdo control control d[3..0] d[7..0] adr[19..0] control d[7..0] adr[19..0] adr[19..0] interface lo g ic (optional) any jta g de vi ce eprom or system memory t o/ fr o m b y teb l asterm v embedded processor embedded system 8 8 4 20 20 20 m ax ? 9 000, m ax 9 000 a , m ax 7 000s, m ax 7 000 a , m ax 7 000 ae , o r m ax 3000 de vi ce c y c lon e f pg a tdi tms trst conf_done nstatus nconfig msel0 msel1 nce tck tdo any c y c lon e, flex 1 0 k , flex 1 0 ka , flex1 0 ke , a p ex 20 k , o r a p ex 20 ke de vi ce 10 k ? 10 k ? v cc v cc v cc gnd data 0 dclk nconfig ( 2 ) ( 2 ) (1) (1) (1) msel1 msel0 v cc 10 k ? v cc 10 k ? 10 k ? gnd
13?36 altera corporation preliminary july 2003 cyclone device handbook, volume 1 other platforms. for more informatio n on the jrunner software driver, see jrunner software driver: an embedded solution to the jtag configuration and the source files on the altera web site. jam stapl jam stapl, jedec standard jesd-71, is a standard file format for in- system programmability (isp) purposes. jam stapl supports programming or configuration of pr ogrammable devices and testing of electronic systems, using the ieee 1149.1 jtag interface. jam stapl is a freely licensed open standard. 1 both jtag connection methods should include space for the masterblaster or byteblastermv header connection. the header is useful during prototyping because it allows you to verify or modify the cyclone fpga?s cont ents. during production, you can remove the header to save cost. program flow the jam player provides an interface for manipulating the ieee std. 1149.1 jtag tap state machine. the tap controller is a 16-state, state machine that is clocked on the rising edge of tck , and uses the tms pin to control jtag operation in a device. figure 13?20 shows the flow of an ieee std. 1149.1 tap co ntroller state machine.
altera corporation 13?37 july 2003 preliminary configuration schemes figure 13?20. jtag tap controller state machine while the jam player provides a driver that manipulates the tap controller, the jam byte-code file ( .jbc ) provides the high-level intelligence needed to program a given device. all jam instructions that select_dr_scan capture_dr shift_dr exit1_dr pause_dr exit2_dr update_dr shift_ir exit1_ir pause_ir exit2_ir update_ir tms = 0 tms = 0 tms = 0 tms = 1 tms = 0 tms = 1 tms = 1 tms = 0 tms = 1 tms = 0 tms = 1 tms = 1 tms = 0 tms = 0 tms = 1 tms = 1 tms = 0 tms = 1 tms = 0 tms = 0 tms = 1 tms = 0 tms = 0 tms = 1 tms = 0 run_test/ idle tms = 0 test_logic/ reset tms = 1 tms = 0 tms = 1 tms = 1 tms = 1 tms = 1 capture_ir select_ir_scan
13?38 altera corporation preliminary july 2003 cyclone device handbook, volume 1 send jtag data to the device involve moving the tap controller through either the data register leg or the instruction register leg of the state machine. for example, loading a jtag instruction involves moving the tap controller to the shift_ir state and shifting the instruction into the instruction register through the tdi pin. next, the tap controller is moved to the run_test/idle state where a delay is implemented to allow the instruction time to be latched. this process is identical for data register scans, except that the data register leg of the state machine is traversed. the high-level jam instructions are the drscan instruction for scanning the jtag data register, the irscan instruction for scanning the instruction register, and the wait command that causes the state machine to sit idle for a specified period of time. each leg of the tap controller is scanned repeatedly, according to instructions in the .jbc file, until all of the target devices are programmed. figure 13?21 illustrates the functional behavi or of the jam player when it parses the .jbc file. when the jam player encounters a drscan , irscan , or wait instruction, it generates the proper data on tck , tms , and tdi to complete the instruction. the flow diagram shows branches for the drscan , irscan , and wait instructions. although the jam player supports other instructions, they are omitted from the flow diagram for simplicity.
altera corporation 13?39 july 2003 preliminary configuration schemes figure 13?21. jam player flow diagram (part 1 of 2) set tms to 1 and pulse tck twice set tms to 0 and pulse tck twice switch case[] eof start switch end eof? test-logic-reset run-test/idle set tms to 1 and pulse tck five times set tms to 0 and pulse tck read instruction from the jam file set tms to 1 and pulse tck three times f t test-logic-reset parse argument irscan drscan switch set tms to 0 and pulse tck delay wait run-test/idle select-ir-scan shift-ir set tms to 0 and pulse tck and write tdi set tms to 0 and pulse tck and write tdi set tms to 1 and pulse tck set tms to 0 and pulse tck set tms to 1 and pulse tck twice set tms to 0 and pulse tck shift-ir exit1-ir pause-ir update-ir run-test/idle shift-dr set tms to 0 and pulse tck and write tdi set tms to 0 and pulse tck twice set tms to 1 and pulse tck parse argument shift-dr select-dr-scan continued on part 2 of flow diagram f t shift-ir
13?40 altera corporation preliminary july 2003 cyclone device handbook, volume 1 figure 13?22. jam player flow diagram (part 2 of 2) execution of a jam program starts at the beginning of the program. the program flow is controlled using goto , call/return , and for/next structures. the goto and call statements refer to labels that are symbolic names for program statements located elsewhere in the jam program. the language itself enforc es almost no constraints on the organizational structure or control flow of a program. 1 the jam language does not support linking multiple jam programs together or including th e contents of another file into a jam program. switch update-ir run-test/idle set tms to 1 and pulse tck set tms to 0 and pulse tck switch update-ir run-test/idle set tms to 1 and pulse tck set tms to 0 and pulse tck set tms to 1 and pulse tck and store tdo set tms to 0 and pulse tck, write tdi, and store tdo shift-dr exit1-dr f f t report error default case[] loop< dr length set tms to 1 and pulse tck and store tdo set tms to 0 and pulse tck, write tdi, and store tdo compare capture exit1-dr switch update-ir run-test/idle set tms to 1 and pulse tck set tms to 0 and pulse tck loop< dr length set tms to 1 and pulse tck and store tdo set tms to 0 and pulse tck and write tdi exit1-dr continued from part 1 of flow diagram correct tdo value t f f t t loop< dr length
altera corporation 13?41 july 2003 preliminary configuration schemes jam instructions each jam statement begins with one of the instruction names listed in table 13?9 . the instruction names, including the names of the optional instructions, are reserved keywords that you cannot use as variable or label identifiers in a jam program. table 13?10 shows the state names that are reserved keywords in the jam language. these keywords correspond to the state names specified in the ieee std. 1149.1 jtag specification. table 13?9. instruction names boolean integer preir call irscan print crc irstop push drscan let return drstop next state exit note wait export pop vector (1) for postdr vmap (1) goto postir - if predr - note to table 13?9 : (1) this instruction name is an optional language extension. table 13?10. reserved keywords (part 1 of 2) ieee std. 1149.1 jtag state names jam reserved state names test-logic-reset reset run-test-idle idle select-dr-scan drselect capture-dr drcapture shift-dr drshift exit1-dr drexit1 pause-dr drpause exit2-dr drexit2 update-dr drupdate select-ir-scan irselect capture-ir ircapture
13?42 altera corporation preliminary july 2003 cyclone device handbook, volume 1 example jam file that reads the idcode the following illustrates the flexibilit y and utility of the jam stapl. the example code reads the idcode out of a single device in a jtag chain. 1 the array variable, i_idcode , is initialized with the idcode instruction bits ordered the lsb first (on the left) to most significant bit (msb) (on the ri ght). this order is important because the array field in the irscan instruction is always interpreted and sent, msb to lsb. example jam file reading idcode boolean read_data[32]; boolean i_idcode[10] = bin 1001101000; ?assumed boolean ones_data[32] = hex ffffffff; integer i; ?set up stop state for irscan irstop irpause; ?initialize device state reset; irscan 10, i_idcode[0..9]; ?load idcode instruction state idle; wait 5 usec, 3 cycles; drscan 32, ones_data[0..31], capture read_data[0..31]; ?capture idcode print ?idcode:?; for i=0 to 31; print read_data[i]; next i; exit 0; shift-ir irshift exit1-ir irexit1 pause-ir irpause exit2-ir irexit2 update-ir irupdate table 13?10. reserved keywords (part 2 of 2) ieee std. 1149.1 jtag state names jam reserved state names
altera corporation 13?43 july 2003 preliminary combining configuration schemes combining configuration schemes this section shows you how to configure cyclone fpgas using multiple configuration schemes on the same board. active serial & jtag you can combine the as configuration scheme with jtag-based configuration. set the msel[1..0] pins to 00 in this setup, as shown in figure 13?23 . this setup uses two 10-pin download cable headers on the board. the first header programs th e serial configuration device in- system via the as programming interface, and the second header configures the cyclone fpga directly via the jtag interface. if you try configuring the device using both schemes simultaneously, jtag configuration takes precedence and as configuration will be terminated.
13?44 altera corporation preliminary july 2003 cyclone device handbook, volume 1 figure 13?23. combining as & jtag configuration notes to figure 13?23 : (1) connect these pull-up resistors to 3.3 v. (2) the nceo pin is left unconnected. (3) you should connect the pull-u p resistor to the same supply voltage as the download cable. (4) v io is a reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable data sheet for this value. passive serial & jtag the ps- and jtag-based configuration are also supported on the same board. set the msel[1..0] pins to 01 in this setup. figure 13?24 shows the pin connections required for co nfiguring cyclone fpgas using ps and jtag interfaces on the same board. the jtag chain only connects to the cyclone fpga in figure 13?24 , but could also connect to the configuration device for in-system programmi ng of that device. if you try configuring the device using both schemes simultaneously, jtag configuration takes precedence and ps configuration will be terminated. masterblaster or byteblastermv 10-pin male header (top view ) v cc (3) vio (4) data dclk ncs asdi data dclk ncso asdo serial configuration device cyclone fpga 10 k ? 10 k ? v cc v cc gnd nceo nce tck tdo tms tdi nstatus nconfig conf_done 10 k ? gnd 10 k ? 10 k ? v cc 10 k ? v cc v cc (1) pin 1 pin 1 10 k ? v cc msel1 msel0 gnd (2) n.c. byteblaster ii 10-pin male header (1) (1) (1)
altera corporation 13?45 july 2003 preliminary device options figure 13?24. combining ps & jtag configuration notes to figure 13?24 : (1) the pull-up resistor should be connected to the same supply voltage as the configuration device. the epc16, epc8, epc4, and epc2 devices? oe and ncs pins have internal, user-configurable pull-up resistors. if you use internal pull-up resistors, do not use extern al pull-up resistors on these pins. (2) the ninit_conf pin is available on epc16, epc8, epc4, and epc2 devices. if ninit_conf is not used, nconfig must be pulled to v cc through a resistor. (3) the nceo pin is left unconnected for the last device in the chain. (4) v io is a reference voltage for the masterblaster output driver. v io should match the device's v ccio . refer to the masterblaster serial/usb communications cable data sheet for this value. (5) connect msel0 to the v cc supply voltage of the i/ o bank it resides in. device options you can set cyclone fpga options in altera?s quartus ii development software using the device & pin options dialog box. select compiler settings (processing menu), then click on the chips & devices tab. figure 13?25 shows the device & pin options dialog box. cyclone device dclk data oe ncs ninit_conf ( 2 ) msel0 msel1 dclk data0 nstatus conf_done nconfig v cc v cc gnd (1) (1) nce nceo n.c. ( 3 ) confi g uration device 10 k ? 10 k ? 10 k ? v cc (5) v cc (1) gnd tck tdo tms tdi v cc (1) gnd p in 1 b y teb l aster ii , masterb l aster, o r b y teb l asterm v 1 0 - p in ma l e h eader gnd vio (4) v cc 10 k ? 10 k ? v cc 10 k ? gnd
13?46 altera corporation preliminary july 2003 cyclone device handbook, volume 1 figure 13?25. configuration options dialog box
altera corporation 13?47 july 2003 preliminary device options table 13?11 summarizes each of these options. table 13?11. cyclone configuration option bits (part 1 of 2) device option option usage default configuration (option off) modified configuration (option on) auto-restart configuration on frame error if a data error occurs during configuration, you can choose how to restart configuration. the configuration process stops until you direct the device to restart configuration. the nstatus pin is driven low when an error occurs. when nconfig is pulled low and then high, the device begins to reconfigure. the configuration process restarts automatically. the nstatus pin drives low and releases. the nstatus pin is then pulled to v cc by the pull- up resistor, indicating that configuration can restart. in the configuration device scheme, if the target device?s nstatus pin is tied to the configuration device?s oe pin, the nstatus reset pulse resets the configuration device automatically. the configuration device then releases its oe pin (which is pulled high) and reconfiguration begins. if an error occurs during passive configuration, the device can be reconfigured without the system having to pulse nconfig . after nstatus goes high, reconfiguration can begin. release clears before tri-states during configuration, the device i/o pins are tri-stated. during initialization, you choose the order for releasing the tri-states and clearing the registers. the device releases the tri- states on its i/o pins before releasing the clear signal on its registers. the device releases the clear signals on its registers before releasing the tri-states. you can use this option to allow the design to operate before it drives out, so all outputs do not start up low. enable chip-wide reset enables a single pin to reset all device registers. chip-wide reset is not enabled. the dev_clrn pin is available as a user i/o pin. chip-wide reset is enabled for all registers in the device. all registers are cleared when the dev_clrn pin is driven low.
13?48 altera corporation preliminary july 2003 cyclone device handbook, volume 1 enable chip-wide output enable enables a single pin to control all device tri-states. chip-wide output enable is not enabled. the dev_oe pin is available as a user i/o pin. chip-wide output enable is enabled for all device tri- states. after configuration, all user i/o pins are tri-stated when dev_oe is low. enable init_done output enables a pin to drive out a signal when the initialization process is complete and the device has entered user mode. the init_done signal is not available. the init_done pin is available as a user i/o pin. the init_done signal is available on the open-drain init_done pin. this pin drives low during configuration. after initialization, it is released and pulled high externally. the init_done pin must be connected to a 10-k ? pull-up resistor. if the init_done output is used, the init_done pin cannot be used as a user i/o pin. data compression enables cyclone fpgas to receive compressed configuration bit stream in active and ps configuration schemes. the quartus ii software generates uncompressed programming files and cyclone fpgas do not decompress data. the quartus ii software generates compressed programming files and cyclone fpgas decompress the bit stream during configuration. table 13?11. cyclone configuration option bits (part 2 of 2) device option option usage default configuration (option off) modified configuration (option on)
altera corporation 13?49 july 2003 preliminary device configuration pins device configuration pins tables 13?12 through 13?14 describe the connections and functionality of all the configuration related pins on the cyclone device. table 13?12 describes the dedicated configuration pins. these pins are required to be connected properly on your board for successful configuration. some of these pins may not be required for your configuration schemes. table 13?12. dedicated cyclone device configuration pins (part 1 of 3) pin name user mode configuration scheme pin type description msel1 msel0 ? all input two-bit configuration input that set the cyclone device configuration scheme (see ta bl e 1 3 ? 2 ). use these pins to select the cyclone configuration schemes for the appropriate connections. these pins must remain at a valid state during power-up before nconfig is pulled low to initiate a reconfiguration and during configuration. nconfig ? all input configuration control input. pulling this pin low during user-mode causes the fpga to lose its configuration data, enter a reset state, and tri-state all i/o pins. returning this pin to a logic high will initiate a reconfiguration. if the configuration scheme uses an enhanced configuration device or epc2 device, the nconfig pin can be tied directly to v cc or to the configuration device's ninit_conf pin.
13?50 altera corporation preliminary july 2003 cyclone device handbook, volume 1 nstatus ? all bidirectional open-drain the device drives nstatus low immediately after power-up and releases it within 5 s. (when using a configuration device, the configuration device holds nstatus low for up to 200 ms.) status output. if an error occurs during configuration, nstatus is pulled low by the target device. status input. if an external source drives the nstatus pin low during configuration or initialization, the target device enters an error state. driving nstatus low after configuration and initialization does not affect the configured device. if the design uses a configuration device, driving nstatus low causes the configuration device to attempt to configure the fpga, but since the fpga ignores transitions on nstatus in user- mode, the fpga will not reconfigure. to initiate a reconfiguration, nconfig must be pulled low. the enhanced configuration devices' and epc2 devices' oe and ncs pins have optional internal programmable pull-up resistors. if the design uses internal pull-up resistors, do not use external 10-k ? pull-up resistors on these pins. conf_done ? all bidirectional open-drain status output. the target device drives the conf_done pin low before and during configuration. once all configuration data is received without error and the initialization clock cycle starts, the target device releases conf_done . status input. after all data is received and conf_done goes high, the target device initializes and enters user mode. driving conf_done low after configuration and initialization does not affect the configured device. the enhanced configuration devices' and epc2 devices' oe and ncs pins have optional internal programmable pull-up resistors. if the design uses internal pull-up resistors, do not use external 10-k ? pull-up resistors on these pins. table 13?12. dedicated cyclone device configuration pins (part 2 of 3) pin name user mode configuration scheme pin type description
altera corporation 13?51 july 2003 preliminary device configuration pins dclk ?ps as input (ps) output (as) in ps configuration, the clock input clocks data from an external source into the target device. data is latched into the fpga on the rising edge of dclk . in as configuration, dclk is an output from the cyclone fpga that provides timing for the configuration interface. after configuration, the logic levels on this pin do not affect the cyclone fpga. asdo i/o in ps mode, n/a in as mode as output control signal from the cyclone fpga to the serial configuration device in as mode used to read out configuration data. ncso i/o in ps mode, n/a in as mode as output output control signal from the cyclone fpga to the serial configuration device in as mode that enables the configuration device. nce ? all input active-low chip enable. the nce pin activates the device with a low signal to allow configuration. the nce pin must be held low during configuration, initialization, and user mode. in single device configuration, tie the nce pin low. in multi-device configuration, the first device?s nce pin is tied low while its nceo pin is connected to nce of the next device in the chain. hold the nce pin low for programming the fpga via jtag. nceo ? all output output that drives low when device configuration is complete. in single device co nfiguration, this pin is left floating. in multi-device configuration, this pin feeds the next device's nce pin. the nceo of the last device in the chain is left floating. data0 ? all input data input. in serial configuration mode, bit-wide configuration data is present ed to the target device on the data0 pin. toggling data0 after configuration does not affect the configured device. table 13?12. dedicated cyclone device configuration pins (part 3 of 3) pin name user mode configuration scheme pin type description
13?52 altera corporation preliminary july 2003 cyclone device handbook, volume 1 table 13?13 describes the optional configuration pins. if these optional configuration pins are not enabled in the quartus ii software, they are available as general-purpose user i/o pins. therefore during configuration, these pins function as user i/o pins and are tri-stated with weak pull-ups. table 13?13. optional cyclone device configuration pins pin name user mode pin type description clkusr n/a if option is on, i/o if option is off input optional user-supplied cloc k input. synchronizes the initialization of one or more devi ces. this pin is enabled by turning on the enable user-supplied start-up clock (clkusr) option in the quartus ii software. init_done n/a if option is on, i/o if option is off output open-drain status pin. can be used to indicate when the device has initialized and is in user mode. the init_done pin must be pulled to v cc with a 10-k ? resistor. the init_done pin drives low during configuration. before and after configuration, the init_done pin is releas ed and is pulled to v cc by an external pull-up resistor. because init_done is tri-stated before configuration, it is pulled high by the external pull-up resistor. thus, the monitoring circuitry must be able to detect a low-to-high transition. this pin is enabled by turning on the enable init_done output option in the quartus ii software. dev_oe n/a if the option is on, i/o if the option is off. input optional pin that allows the us er to override all tri-states on the device. when this pin is dr iven low, all i/o pins are tri- stated; when this pin is driven high, all i/o pins behave as programmed. this pin is enabled by turning on the enable device-wide output enable (dev_oe) option in the quartus ii software. dev_clrn n/a if the option is on, i/o if the option is off. input optional pin that allows you to override all clears on all device registers. when this pi n is driven low, all registers are cleared; when this pin is driven high, all registers behave as programmed. this pin is enabled by turning on the enable device-wide reset (dev_clrn) option in the quartus ii software.
altera corporation 13?53 july 2003 preliminary device configuration files table 13?14 describes the dedicated jtag pins. jtag pins must be kept stable before and during configuratio n to prevent accidental loading of jtag instructions. device configuration files the quartus ii software can create one or more configuration and programming files to support the configuration schemes discussed in this chapter. this section describes these files. sram object file (.sof) you should use an .sof during ps and jtag configuration when the data is downloaded directly from the byteblaster ii, masterblaster, or byteblastermv download cables. for cyclone fpgas, the quartus ii compiler?s assembler module automatically creates the .sof file for each device in your design. the quartus ii software controls the configuration sequence and automatically inserts the appropriate headers into the configuration data stream. all other configuration files are created from the .sof . table 13?14. dedicated jtag pins pin name user mode pin type description tdi n/a input serial input pin for instructions as well as test and programming data. data is shifted in on the rising edge of tck . if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to v cc . tdo n/a output serial data output pin for instructions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. if the jtag interface is not required on the board, the jtag circuitry can be disabled by leaving this pin unconnected. tms n/a input input pin that provides the control signal to determine the transitions of the tap controller state machine. transitions within the state machine occur on the rising edge of tck . therefore, tms must be set up before the rising edge of tck . tms is evaluated on the rising edge of tck . if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to v cc . tck n/a input the clock input to the bst circuitry. some operations occur at the rising edge, while others occur at the falling edge. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to ground.
13?54 altera corporation preliminary july 2003 cyclone device handbook, volume 1 programmer object file (.pof) a .pof is used by the altera prog ramming hardware to program a configuration device, including serial configuration devices and enhanced configur ation devices. a .pof is automaticall y generated when a cyclone project is compiled for the configuration device selected in the configuration dialog box. raw binary file (.rbf) the .rbf is a binary file (e.g., one byte of .rbf data is eight configured bits 10000101 (85 hex)) containing the configur ation data. store data so that the lsb of each data byte is loaded first. a mass storage device can store the converted image. the microprocessor can then read data from the binary file and load it into device. you can also use the microprocessor to perform real-time conv ersion during configuration. in the ps configuration scheme, the data is shifted in serially, lsb first. hexadecimal (intel-format) file (.hex) a .hex file is an ascii file in the in tel hexidecimal format. third-party programmers use this file to program altera's serial configuration devices. microprocessors can also use the .hex file to store and transmit configuration data using th e ps configuration scheme. tabular text file (.ttf) the .ttf file is a tabular ascii file that provides a comma-separated version of the configuration data for the bit-wide ps configuration scheme. in some applications, the storage device containing the configuration data is neither dedicate d to nor connected directly to the target device. for example, a conf iguration device can also contain executable code for a system (e.g., bios routines) and other data. the .ttf allows you to include the configuration data as part of the microprocessor?s source code using the include or source commands. the microprocessor can access this data from a configuration device or mass- storage device and load it into the target device. a .ttf can be imported into nearly any assembly language or high-level language compiler. jam file (.jam) a .jam file is an ascii text file in the jam device programming language that stores device programming info rmation. these files are used to program, verify, and blank-check one or more devices in the quartus ii programmer or in an embedded processor-type environment.
altera corporation 13?55 july 2003 preliminary configuration reliability jam byte-code file (.jbc) a .jbc file is a binary version of a jam file in a byte-code representation. the .jbc file stores device programmin g information used to program, verify, and blank-check one or more devices. configuration reliability the cyclone architecture is designed to minimize the effects of power supply and data noise in a system, and to ensure that the configuration data is not corrupted during co nfiguration or normal user-mode operation. a number of circuit design features ensure the highest possible level of reliability from this sram technology. cyclic redundancy code (crc) circuitry validates each data frame (i.e., sequence of data bits) as it is loaded into the target device. if the crc generated by the device does not match the data stored in the data stream, the configuration process is halted, and the nstatus pin is pulled and held low to indicate an error condit ion. crc circuitry ensures that noisy systems will not cause errors that yield an incorrect or incomplete configuration. the cyclone fpga architecture also provides a very high level of reliability in low-voltage brown-out conditions. cyclone fpga sram blocks require a certain v cc level to maintain accurate data. this voltage threshold is significantly lower than the voltage required to activate the device?s por circuitry. therefore, the target device stops operating if the v cc starts to fail, and indicates an op eration error by pu lling and holding the nstatus pin low. you must then reconfigure the device before it can resume operation as a logic device. in active configuration schemes in which nconfig is tied to v cc , reconfiguration begins as soon as v cc returns to an acceptable level. the low pulse on nstatus resets the configuration device by driving oe low. in passive configuration schemes, the host system starts the reconfiguration process. these device features ensure that cyclone fpgas have the highest possible reliability in a wide variety of environments, and provide the same high level of system reliability that exists in other altera plds. board layout tips even though the dclk signal (used in ps and as configuration schemes) is fairly low-frequency, it drives edge-triggered pins on the cyclone fpga. therefore, any overshoot, unde rshoot, ringing, or other noise can affect configuration. when designing the board, lay out the dclk trace using the same techniques as laying out a clock line, including appropriate buffering. if more th an five devices are used, altera recommends using buffers to split the fan-out on the dclk signal.
13?56 altera corporation preliminary july 2003 cyclone device handbook, volume 1
altera corporation 14?1 october 2003 preliminary 14. serial configuration devices (epcs1 & epcs4) data sheet features the serial configuration devices provide the following features: 1- and 4-mbit flash memory devices that serially configure cyclone tm fpgas using the active serial (as) configuration scheme easy-to-use four-pin interface low cost, low pin count and non-volatile memory low current during configuration and near-zero standby mode current 3.3-v operation available in 8-pin small outline in tegrated circuit (soic) package enables the nios ? processor to access unus ed flash memory through as memory interface re-programmable memory with more than 100,000 erase/program cycles write protection support for memory sectors using status register bits in-system programming support with srunner software driver programming support with byteblaster tm ii download cable additional programming support with the altera ? programming unit (apu) and programming hardware from bp microsystems, system general, and other vendors software design support with the altera quartus ? ii development system for windows-based pcs as well as sun sparc station and hp 9000 series 700/800 delivered with the memory array erased (all the bits set to 1 ) 1 whenever the term ?serial configuration device(s)? is used in this document, it refers to altera epcs1 and epcs4 devices. functional description with sram-based devices such as cyclone fpgas, configuration data must be reloaded each time the device powers up, the system initializes, or when new configuration data is needed. serial configuration devices are flash memory devices with a serial interface that can store c51014-1.2
14?2 altera corporation preliminary october 2003 cyclone device handbook, volume 1 configuration data for a cyclone device and reload the data to the device upon power-up or reconfiguration. table 14?1 lists the serial configuration devices. table 14?2 lists the serial configuration device used with each cyclone fpga and the configuration file size. with the new data-decompression feature in the cyclone fpga family, designers can use smaller serial configuration devices to configure larger cyclone fpgas. 1 serial configuration devices cannot be cascaded. f see chapter 13, configuring cyclone fpgas for more information regarding the cyclone fpga decompression feature in as mode. the serial configuration devices are designed to configure cyclone fpgas and cannot configure other ex isting altera device families. figure 14?1 shows the serial configuration device block diagram. table 14?1. serial configuration devices (3.3-v operation) device memory size (bits) epcs1 1,048,576 epcs4 4,194,304 table 14?2. serial configuration device for cyclone devices cyclone device raw binary configuration file size (bits) (1) serial configuration device epcs1 epcs4 ep1c3 627,376 vv ep1c4 924,512 vv ep1c6 1,167,216 v (2) v ep1c12 2,326,528 v ep1c20 3,559,608 v note to table 14?2 : (1) these are preliminary, uncompressed file sizes. (2) the ep1c6 device?s programming file fi ts in an epcs1 device with compression turned on.
altera corporation 14?3 october 2003 preliminary functional description figure 14?1. serial configuration device block diagram accessing memory in serial configuration devices a designer can access the unused memory locations of the serial configuration device to store or retrieve data through the nios processor and sopc builder. sopc builder is an altera tool for creating bus-based (especially microprocessor-based) systems in altera devices. sopc builder assembles library components like processors and memories into custom microprocessor systems. sopc builder includes the active serial memory interface (asmi) peripheral, an interface core specifical ly designed to work with the serial configuration device. using this core, a designer can create a system with a nios embedded processor that allo ws software access to any memory location within the serial configuration device. control logic i/o shift register memory array status register address counter decode logic data buffer ncs dclk data asdi serial configuration device
14?4 altera corporation preliminary october 2003 cyclone device handbook, volume 1 f for more information on access ing memory within the serial configuration device, see the active serial memory interface data sheet . cyclone fpga configuration cyclone fpgas can be configured with a serial configuration device through the as configuration mode. there are four signals on the serial configuration device that interface directly with the cyclone device?s control signals. the serial configuration device signals data , dclk , asdi , and ncs interface with data0 , dclk , asdo , and ncso control signals on a cyclone fpga, respectively. figure 14?2 shows a serial configuration device programmed via a download cable which configures a cyclone fpga in as mode. figure 14?3 shows a serial configuration device programmed using the apu or a third-party programmer configuring a cyclone fp ga in as configuration mode.
altera corporation 14?5 october 2003 preliminary cyclone fpga configuration figure 14?2. cyclone configuration in as mode (serial co nfiguration device programmed using download cable) data dclk ncs asdi data0 dclk ncso nce nconfig nstatus msel[1..0] nceo conf_done asdo v cc (1) v cc (1) v cc (1) v cc (1) 10 k ? 10 k ? 10 k ? 10 k ? (3) 00 cyclone fpga serial configuration device (2) pin 1 n.c.
14?6 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 14?3. cyclone configuration in as mode (serial configuration device programmed by apu or third- party programmer) notes to figures 14?2 and 14?3 : (1) v cc = 3.3-v. (2) serial configuration devices cannot be cascaded. (3) set msel0 to 0 and msel1 to 0 for as configuration mode. the cyclone fpga acts as the configuration master in the configuration flow and provides the clock to the serial configuration device. the cyclone device enables the serial co nfiguration device by pulling the ncs signal low via the ncso signal (see figures 14?2 and 14?3 ). subsequently, the cyclone fpga sends the instructions and addresses to the serial configuration device via the asdo signal. the serial configuration device responds to the instructions by sending the configuration data to the cyclone fpga?s data0 pin on the falling edge of dclk . the data is latched into the cyclone device on the dclk signal?s rising edge. the cyclone fpga controls the nstatus and conf_done pins during configuration in as mode. if the conf_done signal does not go high at the end of configuration or if the sign al goes high too early, the cyclone fpga will pulse its nstatus pin low to start reconfiguration. upon successful configuration, the cyclone fpga releases the conf_done pin, allowing the external 10-k ? resistor to pull this signal high. initialization begins after the conf_done goes high and completes within 136 clock cycles. after initialization, the cyclone fpga enters user mode. f for more information on configurin g cyclone fpgas in as mode or other configuration modes, see chapter 13, configuring cyclone fpgas . data dclk ncs asdi data0 dclk ncso nce nconfig nstatus msel[1..0] nceo conf_done asdo v cc (1) v cc (1) v cc (1) 10 k ? 10 k ? 10 k ? (3) 00 cyclone fpga serial configuration device (2) n.c.
altera corporation 14?7 october 2003 preliminary serial configuration device memory access multiple cyclone devices can be configured by a single epcs device. however, serial configuration de vices cannot be cascaded. check table 14?1 to ensure the programming file size of the cascaded cyclone fpgas does not exceed the capacity of a serial configuration device. figure 14?4 shows the as configuration scheme with multiple cyclone fpgas in the chain. in as configuration mode, all the devices in the chain must be cyclone devices. the first cyclone device is the configuration master and has its msel[1..0] pins set to as mode. the following cyclone devices are configuration slave devices and have the msel[1..0] pins set to ps mode. figure 14?4. multiple devices in as mode notes to figure 14?4 : (1) v cc = 3.3-v. (2) serial configuration devices cannot be cascaded. (3) set msel0 to 0 and msel1 to 0 to select as mode in the cyclone device. (4) set msel0 to 0 and msel1 to 1 to select ps mode in the cyclone device. serial configuration device memory access this section describes the serial co nfiguration device 's memory array organization and operation codes. timi ng specifications for the memory are provided in the ?timing information? section. data dclk ncs asdi data0 dclk ncso nce nconfig nstatus msel[1..0] nceo conf_done asdo v cc (1) 10 k ? v cc (1) 10 k ? v cc (1) 10 k ? (3) 00 cyclone fpga (master) data0 dclk nce nconfig nstatus msel[1..0] nceo conf_done (4) 01 cyclone fpga (slave) serial configuration device (2) n.c.
14?8 altera corporation preliminary october 2003 cyclone device handbook, volume 1 memory array organization table 14?3 provides details on the memory array organization in epcs4 and epcs1 devices. tables 14?4 and 14?5 show the address range for each sector in the epcs4 and epcs1 devices, respectively. table 14?3. memory array organization in serial configuration devices details epcs4 epcs1 bytes (bits) 524,888 bytes (4 mbits) 131, 072 bytes (1 mbit) number of sectors 8 4 bytes (bits) per sector 65,536 bytes (512 kbits) 32,768 bytes (256 kbits) pages per sector 256 128 total number of pages 2,048 512 bytes per page 256 bytes 256 bytes table 14?4. address range for sectors in epcs4 devices sector address range (byte addresses in hex) start end 7 h'70000 h'7ffff 6 h'60000 h'6ffff 5 h'50000 h'5ffff 4 h'40000 h'4ffff 3 h'30000 h'3ffff 2 h'20000 h'2ffff 1 h'10000 h'1ffff 0 h'00000 h'0ffff
altera corporation 14?9 october 2003 preliminary serial configuration device memory access operation codes this section describes the operations that can be used to access the memory in serial conf iguration devices. the data , dclk , asdi , and ncs signals access to the memory in serial configuration devices. all serial configuration device operation codes, addresses and data are shifted in and out of the device serially, with the most significant bit (msb) first. the device samples the active serial da ta input on the first rising edge of the dclk after the active low chip select ( ncs ) input signal is driven low. shift the operation code (msb first) se rially into the serial configuration device through the active serial data input pin. each operation code bit is latched into the serial configuration device on the rising edge of the dclk . different operations require a different sequence of inputs. while executing an operation, you must shift in the desired operation code, followed by the address bytes, data bytes, both, or neither. the device must drive ncs high after the last bit of the operation sequence is shifted in. table 14?6 shows the operation sequence for every operation supported by the serial configuration devices. for the read byte, read status, and re ad silicon id operations, the shifted- in operation sequence is followed by data shifted out on the data pin. you can drive the ncs pin high after any bit of the data-out sequence is shifted out. for the write byte, erase bulk, erase sector, write enable, write disable, and write status operations, drive the ncs pin high exactly at a byte boundary (drive the ncs pin high a multiple of eight clock pulses after the ncs pin was driven low). otherwise, the operation is rejected and will not be executed. table 14?5. address range for sectors in epcs1 devices sector address range (byte addresses in hex) start end 3 h'18000 h'1ffff 2 h'10000 h'17fff 1 h'08000 h'0ffff 0 h'00000 h'07fff
14?10 altera corporation preliminary october 2003 cyclone device handbook, volume 1 all attempts to access the memory contents while a write or erase cycle is in progress will not be granted, and the write or erase cycle will continue unaffected. write enable operation the write enable operation code is b'0000 0110 , and the most significant bit is listed first. the write enable operation sets the write enable latch bit, which is bit 1 in th e status register. always set the write enable latch bit before write bytes, write status, erase bulk, and erase sector operations. figure 14?5 shows the timing diagram for the write enable operation. figures 14?7 and 14?8 show the status register bit definitions. table 14?6. operation codes for serial configuration devices operation operation code (1) address bytes dummy bytes data bytes dclk f max (mhz) write enable 0000 0110 00 025 write disable 0000 0100 00 025 read status 0000 0101 0 0 1 to infinite (2) 25 read bytes 0000 0011 3 0 1 to infinite (2) 20 read silicon id 1010 1011 0 3 1 to infinite (2) 25 write status 0000 0001 00 125 write bytes 0000 0010 3 0 1 to 256 (3) 25 erase bulk 1100 0111 00 025 erase sector 1101 1000 30 025 notes to table 14?6 : (1) the msb is listed first and the lsb is listed last. (2) the status register, data or silicon id are read out at least once on the data pin and will continuously be read out until ncs is driven high (3) write bytes operation requires at least one data byte on the data pin. if more than 256 bytes are sent to the device, only the last 256 bytes are written to the memory.
altera corporation 14?11 october 2003 preliminary serial configuration device memory access figure 14?5. write enable operation timing diagram write disable operation the write disable operation code is b'0000 0100 , with the msb listed first. the write disable operation resets the write enable latch bit, which is bit 1 in the status register. to prevent the memory from being written unintentionally, the write enable latch bit is automatically reset when implementing the write disable operation as well as under the following conditions: power up write bytes operation completion write status operation completion erase bulk operation completion erase sector operation completion figure 14?6 shows the timing diagram for the write disable operation. figure 14?6. write disable operation timing diagram ncs dclk asdi data 01234567 operation code high impedance ncs dclk asdi data 01234567 operation code high impedance
14?12 altera corporation preliminary october 2003 cyclone device handbook, volume 1 read status operation the read status operation code is b'0000 0101 , with the msb listed first. you can use the read status operation to read the status register. figures 14?7 and 14?8 show the status bits in the status register of both serial configuration devices. figure 14?7. epcs4 status register status bits figure 14?8. epcs1 status register status bits setting the write in progress bit to 1 indicates that the serial configuration device is busy with a write or erase cycle. resetting the write in progress bit to 0 means no write or erase cycle is in progress. resetting the write enable latch bit to 0 indicates that no write or erase cycle will be accepted. set the write enable latch bit to 1 before every write bytes, write status, erase bulk , and erase sector operation. the non-volatile block protect bits determine the area of the memory protected from being written or erased unintentionally. tables 14?7 and 14?8 show the protected area in both serial configuration devices with reference to the block protect bits. the erase bulk operation is only bit 7 bit 0 block protect bits [2..0] write in progress bi t write enable latch bit bp2 bp1 bp0 wel wip bit 7 bit 0 block protect bits [1..0] write in progress bi t write enable latch bit bp1 bp0 wel wip
altera corporation 14?13 october 2003 preliminary serial configuration device memory access available when all the block protect bits are 0 . when any of the block protect bits are set to one, the relevant area is protected from being written by write bytes operations or erased by erase sector operations. the status register can be read at any time, even while a write or erase cycle is in progress. when one of these cycles is in progress, you can check the write in progress bit (bit 0 of the status register) before sending a new operation to the device. the device can also read the status register continuously, as shown in figure 14?9 . table 14?7. block protection bits in epcs4 devices status register content memory content bp2 bit bp1 bit bp0 bit protected area unprotected area 000 none all eight sectors: 0 to 7 001 sector 7 seven sectors: 0 to 6 010 sectors 6 and 7 six sectors: 0 to 5 011 four sectors: 4 to 7 four sectors: 0 to 3 100 all sectors none 101 all sectors none 110 all sectors none 111 all sectors none table 14?8. block protection bits in epcs1 status register content memory content bp1 bit bp0 bit protected area unprotected area 00 none all four sectors: 0 to 3 01 sector 3 three sectors: 0 to 2 10 two sectors: 2 and 3 two sectors: 0 and 1 11 all sectors none
14?14 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 14?9. read status operation timing diagram write status operation the write status operation code is b'0000 0001 , with the msb listed first. use the write status operation to set the status register block protection bits. the write status operation has no effect on the other bits. therefore, designers can implement this operation to protect certain memory sectors, as defined in tables 14?7 and 14?8 . after setting the block protect bits, the protected memory sectors are treated as read-only memory. designers must execute the write enable operation before the write status operation so the device sets the status register?s write enable latch bit to 1. the write status operation is implemented by driving ncs low, followed by shifting in the write status oper ation code and one data byte for the status register on the asdi pin. figure 14?10 shows the timing diagram for the write status operation. ncs must be driven high after the eighth bit of the data byte has been latched in, otherwise, the write status operation is not executed. immediately after ncs is driven high, the device initiates the self-timed write status cycle. the self-timed write status cycle usually takes 5 ms for both serial configuration devices and is guaranteed to be less than 15 ms (see t ws in table 14?10 ). designers must account for this delay to ensure that the status register is writte n with desired block protect bits. alternatively, you can check the write in progress bit in the status register by executing the read status operation while the self-timed write status cycle is in progress. the write in progress bit is 1 during the self-timed write status cycle, and is 0 when it is complete. ncs dclk asdi data 0 1 2 3 4 5 6 7 8 9 101112131415 765432107 2107 6543 operation code msb msb status register out status register out high impedance
altera corporation 14?15 october 2003 preliminary serial configuration device memory access figure 14?10. write status operation timing diagram read bytes operation the read bytes operation code is b'0000 0011 , with the msb listed first. to read the memory contents of the serial configuration device, the device is first selected by driving ncs low. then, the read bytes operation code is shifted-in followed by a 3-byte address ( a[23..0] ). each address bit must be latched-in on the rising edge of the dclk . after the address is latched in, the memory contents of the specified address are shifted out serially on the data pin, beginning with the msb. each data bit is shifted out on the falling edge of dclk . the maximum dclk frequency during the read bytes operation is 20 mhz. figure 14?11 shows the timing diagram for read bytes operation. the first byte addressed can be at an y location. the device automatically increments the address to the next hi gher address after shifting out each byte of data. therefore, the device can read the whole memory with a single read bytes operation. when th e device reaches the highest address, the address counter restarts at 0x000000 , allowing the memory contents to be read out indefinitely until the read bytes operation is terminated by driving ncs high. the device can drive ncs high any time after data is shifted out. if the read bytes operatio n is shifted in while a write or erase cycle is in progress, the operation will not be executed. additionally, it will not have any effect on the write or erase cycle in progress. ncs dclk asdi data 0123456789101112131415 operation code status register 76543210 msb high impedance
14?16 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 14?11. read bytes operation timing diagram note to figure 14?11 : (1) address bits a[23..19] are don't care bits in the epcs4 device. address bits a[23..17] are don't care bits in the epcs1 device. ncs dclk asdi data 012345678910 282930313233343536373839 operation code 24-bit address 23 22 21 3 2 1 0 77 65 43 210 msb msb high impedance data out 1 data out 2
altera corporation 14?17 october 2003 preliminary serial configuration device memory access read silicon id operation the read silicon id operation code is b'1010 1011 , with the msb listed first. this operation reads the serial configuration device?s 8-bit silicon id from the data output pin. if this operation is shifted in during an erase or write cycle, it will be ignored and have no effect on the cycle that is in progress. table 14?9 shows the epcs1 and epcs4 device silicon ids. the device implements the read silicon id operation by driving ncs low then shifting in the read silicon id operation code followed by three dummy bytes on asdi . the serial configuration device?s 8-bit silicon id is then shifted out on the data pin on the falling edge of dclk , as shown in figure 14?12 . the device can terminate the read silicon id operation by driving ncs high after the silicon id has be en read at least once. sending additional clock cycles on dclk while ncs is driven low can cause the silicon id to be shifted out repeatedly. table 14?9. serial configuration device silicon id serial configuration device silicon id (binary value) epcs1 b'0001 0000 epcs4 b'0001 0010
14?18 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 14?12. read silicon id operation timing diagram ncs dclk asdi data 012345678910 282930313233343536373839 operation code three dummy bytes 23 22 21 3 2 1 0 765 43 210 msb msb high impedance silicon id
altera corporation 14?19 october 2003 preliminary serial configuration device memory access write bytes operation the write bytes operation code is b'0000 0010 , with the msb listed first. the write bytes operation allows bytes to be written to the memory. the write enable operation must be executed prior to the write bytes operation to set the write enable latch bit in the status register to 1 . the write bytes operation is implemented by driving ncs low, followed by the write bytes operation code, three address bytes and a minimum one data byte on asdi . if the eight least significant address bits ( a[7..0] ) are not all 0 , all sent data that goes beyond the end of the current page is not written into the next page. instead, this data is written at the start address of the same page (from the address whose eight lsbs are all 0 ). drive ncs low during the entire write bytes operation sequence as shown in figure 14?13 . if more than 256 data bytes are shifted into the serial configuration device with a write bytes operation, the prev iously latched data is discarded and the last 256 bytes are written to the page. however, if less than 256 data bytes are shifted into the serial conf iguration device, they are guaranteed to be written at the specified addres ses and the other bytes of the same page are unaffected. if the design must write more than 256 data bytes to the memory, it needs more than one page of memory. send the write enable and write bytes operation codes followed by three new targeted address bytes and 256 data bytes before a new page is written. ncs must be driven high after the eighth bit of the last data byte has been latched in. otherwise, the device will not execute the write bytes operation. the write enable latch bit in the status register is reset to 0 before the completion of each write bytes operation. therefore, the write enable operation must be carried out before the next write bytes operation. the device initiates the self-timed write cycle immediately after ncs is driven high. the self-timed write cy cle usually takes 1.5 ms for epcs4 devices and 2 ms for epcs1 devices and is guaranteed to be less than 5 ms (see t wb in table 14?10 ). therefore, the designer must account for this amount of delay before another page of memory is written. alternatively, the designer can check the status re gister?s write in progress bit by executing the read status operation wh ile the self-timed write cycle is in progress. the write in progress bit is set to 1 during the self-timed write cycle, and is 0 when it is complete.
14?20 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 14?13. write bytes operation timing diagram note to figure 14?13 : (1) address bits a[23..19] are don't care bits in the epcs4 device. address bits a[23..17] are don't care bits in the epcs1 device. ncs dclk asdi 012345678910 2829303132333435363738394041424344454647 2072 2073 2074 2075 2076 2077 2078 2079 operation code 24-bit address 23 22 21 3 2 1 0 7654 msb msb msb msb data byte 1 data byte 2 data byte 256 3210 7654 7654 3210 3210
altera corporation 14?21 october 2003 preliminary serial configuration device memory access erase bulk operation the erase bulk operation code is b'1100 0111 , with the msb listed first. the erase bulk operation sets all memory bits to 1 or 0xff . similar to the write bytes operation, the write enable operation must be executed prior to the erase bulk operation so that the write enable latch bit in the status register is set to 1 . designers implement the erase bulk operation by driving ncs low and then shifting in the erase bulk operation code on the asdi pin. ncs must be driven high after the eighth bit of the erase bulk operation code has been latched in. figure 14?14 shows the timing diagram. the device initiates the self-timed erase bulk cycle immediately after ncs is driven high. the self-timed erase bulk cycle usually takes 5 s for epcs4 devices (guaranteed to be less than 10 s) or 3 s for epcs1 devices (guaranteed to be less than 6 s). see t eb in table 14?10 . designers must account for this delay before accessing the memory contents. alternatively, designers can check the write in progress bit in the status register by executing the read status operation while the self-timed erase cycle is in progress. the write in progress bit is 1 during the self-timed erase cycle and is 0 when it is complete. the write enable latch bit in the status register is reset to 0 before the erase cycle is complete. figure 14?14. erase bulk operation timing diagram erase sector operation the erase sector operation code is b'1101 1000 , with the msb listed first. the erase sector operation allows the user to erase a certain sector in the serial configuration device by setting all bits inside the sector to 1 or 0xff . this operation is useful for users who access the unused sectors as general purpose memory in their applications. the write enable operation must be executed prior to the erase sector operation so that the write enable latch bit in the status register is set to 1 . ncs dclk asdi 01234567 operation code
14?22 altera corporation preliminary october 2003 cyclone device handbook, volume 1 the erase sector operation is implemented by first driving ncs low, then shifting in the erase sector operation code and the three address bytes of the chosen sector on the asdi pin. the three address bytes for the erase sector operation can be any address inside the specified sector. (see tables 14?4 and 14?5 for sector address range information.) drive ncs high after the eighth bit of the erase sector operation code has been latched in. figure 14?15 shows the timing diagram. immediately after the device drives ncs high, the self-timed erase sector cycle is initiated. the self-timed erase sector cycle usually takes 2 s for epcs1 and epcs4 devices and is guaranteed to be less than 3 s for both serial configuration devices. you must account for this amount of delay before the memory contents can be accessed. alternatively, you can check the write in progress bit in the status register by executing the read status operation while the erase cycle is in progress. the write in progress bit is 1 during the self-timed erase cycle and is 0 when it is complete. the write enable latch bit in the status register is reset to 0 before the erase cycle is complete. figure 14?15. erase sector operation timing diagram power & operation this section describes the power modes, power-on reset (por) delay, error detection, and initial programmi ng state of serial configuration devices. power mode serial configuration devices support active power and standby power modes. when ncs is low, the device is enabled and is in active power mode. the cyclone fpga is configured while in active power mode. when ncs is high, the device is disabled but could remain in active power mode until all internal cycles have completed (such as write or erase operations). the serial configuratio n device then goes into stand-by ncs dclk asdi 0123456789 28293031 operation code 24-bit address 23 22 3 2 1 0 msb
altera corporation 14?23 october 2003 preliminary timing information power mode. the i cc1 parameter specifies the v cc supply current when the device is in active power mode and the i cc0 parameter specifies the current when the device is in stand-by power mode (see table 14?16 ). power-on reset during initial power-up, a por delay oc curs to ensure the system voltage levels have stabilized. during as configuration, the cyclone fpga controls the configuration and has a longer por delay than the serial configuration device. therefore, the por delay is governed by the cyclone fpga (typically 100 ms). error detection during as configuration with the serial configuration device, the cyclone fpga monitors the conf iguration status through the nstatus and conf_done pins. if an error condition occurs ( nstatus drives low) or if the conf_done pin does not go high, the cyclone fpga will initiate reconfiguration by pulsing the nstatus and ncso signals, which controls the chip select pin on the serial configuration device ( ncs ). after an error, configuration automatically restarts if the auto-restart upon frame error option is turned on in the quartus ii software. if the option is turned off, the system must monitor the nstatus signal for errors and then pulse the nconfig signal low to restart configuration. timing information figure 14?16 shows the timing waveform for write operation to the serial configuration device. figure 14?16. write operation timing ncs dclk asdi data t ncsh t dsu t ncssu t ch t cl t csh t dh bit n bit 0 bit n ? 1 high impedance
14?24 altera corporation preliminary october 2003 cyclone device handbook, volume 1 table 14?10 defines the serial co nfiguration device ti ming parameters for write operation. figure 14?17 shows the timing waveform fo r the serial configuration device's read operation. table 14?10. write operation parameters symbol parameter min max unit f wclk write clock frequency (from cyclone fpga, byteblaster ii cable or embedded processor) for write enable, write disable, read status, read silicon id, write bytes, erase bulk, and erase sector operations 25 mhz t ch dclk high time 20 ns t cl dclk low time 20 ns t ncssu chip select ( ncs ) setup time 10 ns t ncsh chip select ( ncs ) hold time 10 ns t dsu data ( asdi ) in setup time before rising edge on dclk 5ns t dh data ( asdi ) hold time after rising edge on dclk 5ns t csh chip select high time 100 ns t wb_epcs1 (1) write bytes cycle time for epcs1 devices 25ms t wb_epcs4 (1) write bytes cycle time for epcs4 devices 1.5 5 ms t ws (1) write status cycle time 5 15 ms t eb_epcs1 (1) erase bulk cycle time for epcs1 devices 36s t eb_epcs4 (1) erase bulk cycle time for epcs4 devices 510s t es (1) erase sector cycle time 2 3 s note to table 14?10 : (1) these parameters are not shown in figure 14?16 .
altera corporation 14?25 october 2003 preliminary timing information figure 14?17. read operation timing table 14?11 defines the serial configuratio n device timing parameters for read operation. ncs dclk data asdi t nclk2d t cl t ch t odis bit n bit 0 bit n ? 1 add_bit 0 table 14?11. read operation parameters symbol parameter min max unit f rclk read clock frequency (from cyclone fpga or embedded processor) for read bytes operation 20 mhz t ch dclk high time 25 ns t cl dclk low time 25 ns t odis output disable time after read 15 ns t nclk2d clock falling edge to data 15 ns
14?26 altera corporation preliminary october 2003 cyclone device handbook, volume 1 figure 14?18 shows the timing waveform for cyclone fpga as configuration scheme using a serial configuration device. figure 14?18. as configuration timing table 14?12 shows the timing parameters for as configuration mode. programming & configuration file support the quartus ii design software provides programming support for serial configuration devices. after selecting the serial configuration device, the quartus ii software automatically gene rates the programmer object file ( .pof ) to program the device. the software allows users to select the appropriate serial configuration devi ce density that most efficiently stores the configuration data for a selected cyclone fpga. read address bit n ? 1 bit n bit 1 bit 0 t h t cl t ch t su 136 cycles nstatus nconfig conf_done ncso dclk asdo data0 init_done user i/o user mode t por table 14?12. timing parameters for as configuration symbol parameter min typ max unit f clk dclk frequency (from cyclone fpga) 15 20 mhz t ch dclk high time 25 ns t cl dclk low time 25 ns t h data hold time after rising edge on dclk 0 ns t su data set up time before rising edge on dclk 5 ns t por por delay 100 ms
altera corporation 14?27 october 2003 preliminary operating conditions the serial configuration device can be programmed in-system by an external microprocessor using srunne r. srunner is a software driver developed for embedded serial conf iguration device programming that designers can customize to fit in different embedded systems. the srunner can read a raw pr ogramming data file ( .rpd ) and write to the serial configuration devices. the prog ramming time is comparable to the quartus ii software programming time. f for more information about srunner, see the srunner: an embedded solution for serial configuration device programming white paper and the source code on the altera web site ( www.altera.com ). serial configuration devices can be programmed using the apu with the appropriate programming adapter (plmsepc-8) via the quartus ii software or the byteblaster ii downlo ad cable via the quartus ii software. in addition, many third-party prog rammers, such as bp microsystems and system general, offer programm ing hardware that supports serial configuration devices. during in-system programming of a se rial configuration device via the byteblaster ii download cable, the cable pulls nconfig low to reset the cyclone device and overrides the 10-k ? pull-down resistor on the cyclone device?s nce pin (see figure 14?2 ). the download cable then uses the four interface pins ( data , ncs , asdi , and dclk ) to program the serial configuration device. once the programming is complete, the download cable releases the serial co nfiguration device?s four interface pins and the cyclone device?s nce pin, and pulses nconfig to start configuration. f for more information on programming and configuration support, see the following documents: altera programming hardware data sheet programming hardware manufacturers byteblaster ii parallel port download cable data sheet operating conditions tables 14?13 through 14?17 provide information on absolute maximum ratings, recommended operating cond itions, dc operating conditions, and capacitance for serial configuration devices. table 14?13. absolute maximum ratings note (1) (part 1 of 2) symbol parameter condition min max unit v cc supply voltage with respect to ground ? 0.6 4.0 v v i dc input voltage with respect to ground ? 0.6 4.0 v
14?28 altera corporation preliminary october 2003 cyclone device handbook, volume 1 i max dc v cc or gnd current 15 ma i out dc output current per pin ? 25 25 ma p d power dissipation 54 mw t stg storage temperature no bias ? 65 150 c t amb ambient temperature under bias ? 65 135 c t j junction temperature under bias 135 c table 14?14. recommended operating conditions symbol parameter conditions min max unit v cc supply voltage (2) 3.0 3.6 v v i input voltage respect to gnd ? 0.3 0.3 + v cc v v o output voltage 0 v cc v t a operating temperature for commercial use 0 70 c for industrial use ? 40 85 c t r input rise time 5 ns t f input fall time 5 ns table 14?15. dc operating conditions symbol parameter conditions min max unit v ih high-level input voltage 0.7 v cc v cc + 0.4 v v il low-level input voltage ? 0.5 0.3 v cc v v oh high-level output voltage i oh = ? 100 a (3) v cc ? 0.2 v v ol low-level output voltage i ol = 1.6 ma (3) 0.4 v i i input leakage current v i = v cc or gnd ? 10 10 a i oz tri-state output off-state current v o = v cc or gnd ? 10 10 a table 14?16. i cc supply current symbol parameter conditions min max unit i cc0 v cc supply current (standby) 50 a i cc1 v cc supply current (during active power mode) 514ma table 14?13. absolute maximum ratings note (1) (part 2 of 2) symbol parameter condition min max unit
altera corporation 14?29 october 2003 preliminary pin information pin information as shown in figure 14?19 , the serial configuration device is an 8-pin device. the control pins on the serial configuration device are: serial data output ( data ), active serial data input ( asdi ), serial clock ( dclk ), and chip select ( ncs ). table 14?18 shows the serial conf iguration device's pin descriptions. figure 14?19 shows the altera serial configuration device 8-pin soic package and its pin-out diagram. figure 14?19. altera serial configuration device package pin-out diagram table 14?17. capacitance note (4) symbol parameter conditions min max unit c in input pin capacitance v in = 0 v 6 pf c out output pin capacitance v out = 0 v 8 pf notes to table 14?13 through 14?17 : (1) see the operating requirements for altera devices data sheet . (2) maximum v cc rise time is 100 ms. (3) the i oh parameter refers to high-level ttl or cmos output current; the i ol parameter refers to low-level ttl or cmos output current. (4) capacitance is sample-tested only at t a = 25 c and at a 20-mhz frequency. v cc v cc dclk asdi v cc gnd ncs data epcs1 or epcs4 device 1 2 3 4 8 7 6 5 table 14?18. serial configuration device pin description (part 1 of 2) pin name pin number pin type description data 2 output the data output signal transfers data serially out of the serial configuration device to the cycl one fpga during read/configuration operation. during a read/configuration operations, the serial configuration device is enabled by pulling ncs low. the data signal transitions on the falling edge of dclk . asdi 5 input the as data input signal is used to transfer data serially into the serial configuration device. it receives the data that should be programmed into the serial configuration device. data is latched in the rising edge of dclk .
14?30 altera corporation preliminary october 2003 cyclone device handbook, volume 1 package all serial configuration devices are available in 8-pin plastic soic package. f for more information on altera device packaging, see chapter 6, package information for cyclone devices , including mechanical drawing and specifications for this package. ordering code table 14?19 shows the ordering codes for serial configuration devices. ncs 1 input the active low chip select input signal toggles at the beginning and end of a valid instruction. when this signal is high, the device is deselected and the data pin is tri-stated. when this signal is low, it enables the device and puts the device in an active mode. after power up, the serial configurati on device requires a falling edge on the ncs signal before beginning any operation. dclk 6 input dclk is provided by the cyclone fp ga. this signal provides the timing of the serial interface. the data presented on asdi is latched to the serial configuration device, at the rising edge of dclk . data on the data pin changes after the falling edge of dclk and is latched into the cyclone fpga on the rising edge. vcc 3, 7, 8 power power pins connect to 3.3 v. gnd 4 ground ground pin. table 14?18. serial configuration device pin description (part 2 of 2) pin name pin number pin type description table 14?19. serial configuration device ordering codes device ordering code epcs1 epcs1si8 epcs4 epcs4si8
altera corporation index?1 preliminary index 1.5-v devices board layout 12?21 choose a regulator type 12?9 designing with 12?1 linear voltage regulators 12?4 maximum output current 12?8 power sequencing & hot socketing 12?1 regulator application examples 12?19 regulator circuits 12?10 selecting voltage regulators 12?8 split-plane method 12?23 switching voltage regulators 12?6 synchronous switching regulator example 12?20 using multivolt i/o pins 12?2 voltage divider network 12?10 voltage regulators 12?3 a architecture addnsub signal 2?7 bus hold 2?51 byte enables 2?23 carry-select chain 2?10 clear & preset logic control 2?12 clock clock feedback 2?37 clock mode independent 2?25 input/output 2?25 read/write 2?27 clock multiplication & division 2?35 dual-purpose clock pins 2?30 external clock inputs 2?36 external clock outputs 2?36 global clock network 2?29 global clock network & phase-locked loops 2?29 maximum input & output clock rates 4?29 phase shifting 2?37 combined resources 2?31 configuration 3?5 schemes 3?6 testing 3?1 control signals 2?38 control signals & m4k interface 2?23 cyclone architecture 2?1 dc & switching characteristics 4?1 device pin-outs 5?1 dynamic arithmetic mode 2?9 embedded memory 2?18 functional description 2?1 i/o standard advanced i/o standard support 2?52 external i/o delay parameters 4?23 i/o structure 2?39 lvds i/o pins 2?54 multivolt i/o interface 2?54 ieee std. 1149.1 (jtag) boundary scan support 3?1 lab control signals 2?4 interconnects 2?3 lock detect signal 2?37 logic array blocks 2?3 logic elements 2?5 operating modes 2?7 lut chain & register chain 2?7 memory configuration sizes 2?21 ddr sdram & fcram 2?46 external ram interfacing 2?46 modes 2?18 multitrack interconnect 2?12 normal mode 2?8 open-drain output 2?50 operating conditions 4?1 operating modes 3?6
index?2 altera corporation preliminary cyclone fpga device handbook ordering information 5?1 parity bit support 2?20 plls 2?32 power consumption 4?8 power sequencing & hot socketing 2?55 programmable drive strength 2?49 programmable duty cycle 2?38 programmable pull-up resistor 2?51 reference & ordering information 5?1 shift register support 2?20 signaltap ii embedded logic analyzer 3?5 single-port mode 2?28 slew-rate control 2?50 software 5?1 timing external timing parameters 4?16 internal timing parameters 4?11 model 4?9 preliminary & final 4?9 c configuration active serial & jtag 13?43 active serial configuration (serial configu- ration devices) 13?7 combining configuration schemes 13?43 configuring cyclone fpgas 13?1 fpgas with jrunner 13?35 fpgas with the microblaster software 13?26 configuring multiple cyclone fpgas 13?18 configuring multiple devices (cascading) 13?10 connecting the jtag chain to the embedded processor 13?34 data compression 13?3 device configuration overview 13?1 device configuration files 13?53 device options 13?45 jam example jam file that reads the idcode 13?42 instructions 13?41 stapl 13?36 jtag configuration of multiple devices 13?32 jtag configuration using a download cable 13?29 jtag-based configuration 13?28 passive serial 13?15 passive serial & jtag 13?44 program flow 13?36 programming config uration devices 13?20 programming serial configuration devices 13?13 ps configuration from a microprocessor 13?25 ps configuration using a download cable 13?21 ps configuration using configuration device 13?15 quartus ii software board layout tips 13?55 configuration reliability 13?55 hexadecimal (intel-format) file (.hex) 13?54 jam byte-code file (.jbc) 13?55 jam file (.jam) 13?54 programmer object file (.pof) 13?54 raw binary file (.rbf) 13?54 sram object file (.sof) 13?53 tabular text file (.ttf) 13?54 schemes 13?6 timing passive serial timing 13?26 d device configuration pins 13?49 i i/o standards 11?1 1.5-v lvcmos normal & wide voltage ranges (eia/jedec standard jesd8- 11) 8?5 1.8-v
altera corporation index?3 preliminary lvcmos normal & wide voltage ranges (eia/jedec standard eia/jesd8- 7) 8?4 lvttl normal & wide voltage ranges (eia/jedec standard eia/jesd8- 7) 8?4 2.5-v lvcmos normal & wide voltage ranges (eia/jedec standard eia/jesd8- 5) 8?4 lvttl normal & wide voltage ranges (eia/jedec standard eia/jesd8- 5) 8?3 3.3-v (pci special interest group (sig) pci lo- cal bus specification revision 2.2) 8?5 lvcmos (eia/jedec standard jesd8- b) 8?3 lvttl (eia/jedec standard jesd8- b) 8?2 bidirectional pads 8?15 cyclone i/o banks 8?9 dc guidelines 8?17 differential i/o standard termination 8?14 differential pad placement guidelines 8?14 differential sstl-2 - eia/jedec standard jesd8-9a 8?9 hot socketing 8?13 i/o termination 8?13 input pads 8?15 lvds (ansi/tia/eia standard an- si/tia/eia-644) 8?8 output pads 8?15 pad placement & dc guidelines 8?14 programmable current drive strength 8?12 quartus ii software assigning pins 8?19 auto placement & verification of select- able i/o standards 8?21 compiler settings 8?18 device & pin options 8?18 i/o banks in the floorplan view 8?20 programmable drive strength settings 8?20 software support 8?18 sstl-2 class i & ii (eia/jedec standard jesd8-9a) 8?7 sstl-3 class i & ii (eia/jedec standard jesd8-8) 8?7 supported i/o standards 8?2 using selectable i/o standards in cyclone devices 8?1 voltage-referenced i/o standard termination 8?14 voltages 5.0-v device compatibility 11?3 devices can be driv en before power- up 11?6 hot-socketing 11?6 i/o pins remain tri-stated during power- up 11?6 multivolt i/o operation 11?2 power-on reset 11?7 power-up sequence 11?7 signal pins do not drive the vccio or vccint power supplies 11?6 vref pad placement guidelines 8?14 l lvds clock domains 9?3 cyclone i/o banks 9?2 cyclone i/o interface 9?3 cyclone receiver & transmitter termination 9?15 implementing lvds in cyclone devices 9?1 quartus ii software board design considerations 9?26 capturing serial data on cyclone lvds inputs 9?18 design guidelines 9?25 differential pad placement guidelines 9?25 implementing cyclone lvds i/o pins in the quartus ii software 9?16 receiver circuit 9?19 transmitter circuit 9?17 transmitting serial data on cyclone lvds outputs 9?16 receiver & transmitter 9?4
index?4 altera corporation preliminary cyclone fpga device handbook timing in cyclone devices 9?10 m memory bidirectional double data rate 10?3 ddr memory support 10?4 double data rate input 10?1 output 10?2 implementing double data rate i/o signal- ing in cyclone devices 10?1 p pll altpll compilation report 6?31 input ports 6?22 megawizard customization 6?23 megawizard page description 6?25 output ports 6?23 simulation 6?37 timing analysis 6?33 areset 6?12 board layout 6?17 clock combined sources 6?41 dedicated clock input pins 6?40 dual-purpose clock i/o pins 6?40 external clock output 6?11 feedback modes 6?13 global clock network 6?38 multiplication & division 6?8 control signals 6?12 cyclone pll blocks 6?2 hardware features 6?8 hardware overview 6?1 jitter considerations 6?19 modes no compensation 6?15 normal 6?13 zero delay buffer 6?14 partitioned vcca island within vccint plane 6?17 pfdena 6?12 phase shifting 6?9 pins 6?16 pins & clock network connections 6?6 pllena 6?12 programmable duty cycle 6?10 quartus ii altpll megafunction 6?20 separate vcca power plane 6?17 software support 6?20 specifications 6?20 thick vcca traces 6?18 using plls in cyclone devices 6?1 vcca & gnda 6?17 s serial configuration devices (epcs1 & epcs4) data sheet 14?1 accessing memory 14?3 cyclone fpga configuration 14?4 error detection 14?23 features 14?1 functional description 14?1 operating conditions 14?27 ordering code 14?30 package 14?30 pin description 14?29 power & operation 14?22 power mode 14?22 power-on reset 14?23 programming & configuration file support 14?26 software overview 6?4 u using cyclone devices in multiple-voltage systems 11?1
altera part number search literature licensing buy on-line download home | products | support | system solutions | technology center | education & events | corporate | buy on-line results for: ep1c3t100 4 part numbers found and 0 obsolete part numbers found cyclone device family (1.5v) cyclone datasheet cyclone literature part number format buying altera devices part number device pin & package temperature speeds options ep1c3t100c6 ep1c3t100c7 ep1c3t100c8 ep1c3 100 pin tqfp commercial ( 0 to 85c) 6, 7, 8 none ep1c3t100i7 ep1c3 100 pin tqfp industrial ( -40 to 100c) 7 none advanced help please give us feedback sign up for e-mail updates home | products | support | system solutions | technology center | education & events | corporate | buy on-line contact us | new user | site map | privacy | legal notice copyright ? 1995-2004 altera corporation, 101 innovation drive, san jose, california 95134, usa http://www.altera.com/cgi-bin/devsearch.pl?searcht...l=corp&qt=ep1c3t100&scope=0&submit.x=36&submit.y=7 [9/20/2004 11:16:26 am]
industrial temperature device support altera home page global navigation button literature global navigation button licensing global navigation button buy on- line global navigation button download home | products | support | system solutions | technology center | education & events | corporate | buy on-line devices | design software | intellectual property | design services | dev. kits/cables | literature choose your device fpga vs asic calculator device family overview performance advantages fpgas stratix ii stratix cyclone ii cyclone stratix gx apex ii apex 20k mercury flex 10k acex 1k flex 6000 cplds max ii max 3000a max 7000 structured asics about hardcopy hardcopy stratix hardcopy apex 20k home > products > devices > industrial print this page e-mail this page industrial temperature device support altera is committed to supporting the industrial device needs of its customers. the industrial temperature range guarantees a device to be fully functional from -40oc to +100oc (junction) [-40oc to +105oc (junction) for max devices]. these devices go through extensive product characterization and reliability stresses to ensure functionality under extreme temperature variations. altera offers a wide range of industrial devices in all device families. table 1 shows the products currently offered in the industrial temperature range. for additional details regarding industrial temperature offerings not shown below, contact your local sales office or distributor. table 1. industrial temperature device offerings (click on the product name for more details.) supply voltage device max ? ii stratix? cyclone? apex? mercury? flex ? acex ? max configuration devices 1.5 v stratix cyclone apex ii 1.8 v max iig apex 20kc apex 20ke mercury 2.5 v max ii apex 20k flex 10ke acex 1k max 7000b file:///p|/alte.htm (1 of 14) [1/18/2005 11:17:25 am]
industrial temperature device support configuration devices enhanced configuration serial configuration embedded processors about excalibur excalibur devices market-specific offerings lead-free extended temperature industrial mature devices flex 8000 max 9000 classic 3.3 v max ii flex 10ka flex 6000 max 7000a max 3000a 440 kbit 1 mbit 2 mbit 4 mbit 8 mbit 16 mbit 5.0 v flex 10k ? flex 8000 max 7000 max 7000s max 9000 classic 65 kbit 200 kbit 440 kbit 1 mbit 2 mbit back to top table 2. max ii industrial support (coming soon!) device package (1) speed grade epm240 epm240g 100-pin tqfp -5 epm570 epm570g 100-pin tqfp 144-pin tqfp 256-pin fineline bga ? -5 epm1270 epm1270g 144-pin tqfp 256-pin fineline bga -5 epm2210 epm2210g 256-pin fineline bga 324-pin fineline bga -5 back to top table 3. stratix industrial support device package (1) speed grade ep1s10 484-pin fineline bga 672-pin fineline bga 780-pin fineline bga -6 -7 -6 file:///p|/alte.htm (2 of 14) [1/18/2005 11:17:26 am]
industrial temperature device support ep1s20 484-pin fineline bga 672-pin fineline bga 780-pin fineline bga -6 -7 -6 ep1s25 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga -7 -6 -6 ep1s30 1,020-pin fineline bga -6 ep1s40 1,020-pin fineline bga -6 ep1s60 1,020-pin fineline bga -6 ep1s80 1,020-pin fineline bga -7 back to top table 4. cyclone industrial temperature support device package (1) speed grade ep1c3 100-pin tqfp 144-pin tqfp -7 ep1c4 324-pin fineline bga 400-pin fineline bga -7 ep1c6 144-pin tqfp 240-pin pqfp 256-pin fineline bga -7 ep1c12 240-pin pqfp 256-pin fineline bga 324-pin fineline bga -7 ep1c20 324-pin fineline bga 400-pin fineline bga -7 back to top table 5. apex ii industrial temperature support device package (1) speed grade ep2a15 672-pin fineline bga -8 file:///p|/alte.htm (3 of 14) [1/18/2005 11:17:26 am]
industrial temperature device support ep2a25 672-pin fineline bga 724-pin bga -8 ep2a40 724-pin bga 1,020-pin fineline bga -8 back to top table 6. apex 20kc industrial support device package (1) speed grade ep20k200c 484-pin fineline bga -8 ep20k400c 652-pin bga 672-pin fineline bga -8 ep20k600c 652-pin bga 672-pin fineline bga -8 ep20k1000c 1,020-pin fineline bga -8 back to top table 7. apex 20ke industrial temperature support device package (1) speed grade ep20k30e 144-pin fineline bga -2x ep20k60e 324-pin fineline bga -2x ep20k60e 144-pin fineline bga 324-pin fineline bga 208-pin pqfp -2x ep20k100e 144-pin fineline bga 324-pin fineline bga 356-pin bga 240-pin pqfp -2x ep20k160e 484-pin fineline bga -2x ep20k200e 240-pin pqfp -2 file:///p|/alte.htm (4 of 14) [1/18/2005 11:17:26 am]
industrial temperature device support ep20k200e 484-pin fineline bga 672-pin fineline bga 356-pin bga 240-pin pqfp -2x ep20k300e 672-pin fineline bga 652-pin bga 240-pin pqfp -2x ep20k400e 652-pin bga 672-pin fineline bga -2x ep20k600e 652-pin bga 672-pin fineline bga -2 back to top table 8. apex 20k industrial temperature support device package (1) speed grade ep20k100 208-pin pqfp 240-pin pqfp -2v ep20k100 208-pin pqfp 240-pin pqfp -2 ep20k200 240-pin pqfp 484-pin fineline bga -2v ep20k200 240-pin pqfp -2 ep20k400 652-pin bga -2 ep20k400 672-pin fineline bga -2v back to top table 9. mercury industrial temperature support device package (1) speed grade ep1m120 484-pin fineline bga -6 ep1m350 780-pin fineline bga -6 file:///p|/alte.htm (5 of 14) [1/18/2005 11:17:26 am]
industrial temperature device support back to top table 10. flex 10ke industrial temperature support device package (1) speed grade epf10k30e 144-pin tqfp 208-pin pqfp 256-pin fineline bga -2 epf10k50e 144-pin tqfp, 240-pin pqfp 256-pin fineline bga -2 epf10k50s 208-pin pqfp 484-pin fineline bga -2 epf10k100e 208-pin pqfp 256-pin fineline bga 484-pin fineline bga -2 epf10k130e 240-pin pqfp 356-pin bga 484-pin fineline bga -2 epf10k200e 600-pin bga -2 epf10k200s 356-pin bga 672-pin fineline bga -2 back to top table 11. flex 10ka industrial temperature support device package (1) speed grade epf10k10a 144-pin tqfp 208-pin pqfp -3 epf10k30a 256-pin fineline bga -2 144-pin tqfp 208-pin pqfp 356-pin bga -3 file:///p|/alte.htm (6 of 14) [1/18/2005 11:17:26 am]
industrial temperature device support epf10k50v 240-pin pqfp -2 240-pin pqfp 356-pin bga -3 240-pin pqfp 600-pin bga -4 epf10k100a 240-pin pqfp 356-pin bga -3 back to top table 12. flex 6000 industrial temperature support device package (1) speed grade epf6010a 100-pin tqfp -2 epf6016 144-pin tqfp 208-pin pqfp -2 144-pin tqfp -3 epf6016a 144-pin tqfp 208-pin pqfp -3 epf6024a 208-pin pqfp 256-pin bga 256-pin fineline bga -2 back to top table 13. flex 10k industrial temperature device package (1) speed grade epf10k10 84-pin plcc 144-pin tqfp 208-pin pqfp -4 epf10k20 144-pin tqfp 208-pin pqfp 240-pin pqfp -4 file:///p|/alte.htm (7 of 14) [1/18/2005 11:17:26 am]
industrial temperature device support epf10k30 208-pin pqfp 240-pin pqfp -4 epf10k50 240-pin pqfp -4 back to top table 14. flex 8000 industrial temperature device package (1) speed grade epf81188a 208-pin pqfp -4 epf81188a 208-pin pqfp -3 epf81188a 240-pin rqfp -4 epf81500a 240-pin rqfp -3 epf8282a 84-pin plcc -4 epf8282a 100-pin tqfp -3 epf8452a 84-pin plcc -4 epf8452a 160-pin rqfp -3 epf8636a 84-pin plcc -4 epf8820a 208-pin rqfp -4 back to top table 15. acex 1k industrial temperature support device package (1) speed grade ep1k10 100-pin tqfp 256-pin fineline bga -2 ep1k30 144-pin tqfp 256-pin fineline bga -2 ep1k50 144-pin tqfp, 208-pin pqfp 256-pin fineline bga -2 file:///p|/alte.htm (8 of 14) [1/18/2005 11:17:26 am]
industrial temperature device support ep1k100 208-pin pqfp 256-pin fineline bga 484-pin fineline bga -2 back to top table 16. max 7000b industrial support device package (1) speed grade epm7032b 44-pin tqfp -5 epm7064b 44-pin tqfp 100-pin tqfp -5 epm7128b 100-pin fineline bga 100-pin tqfp 256-pin fineline bga -7 epm7256b 100-pin tqfp 208-pin pqfp 256-pin fineline bga -7 back to top table 17. max 7000a industrial support device package (1) speed grade epm7032ae 44-pin tqfp -7 epm7064ae 44-pin plcc 44-pin tqfp 100-pin tqfp -7 epm7128ae 100-pin fineline bga 100-pin tqfp 144-pin tqfp -7 epm7128a 100-pin tqfp 144-pin tqfp -10 file:///p|/alte.htm (9 of 14) [1/18/2005 11:17:26 am]
industrial temperature device support epm7256ae 100-pin fineline bga 100-pin tqfp 144-pin tqfp 208-pin pqfp 256-pin fineline bga -7 epm7256a 144-pin tqfp 208-pin pqfp 256-pin bga -10 epm7512ae 208-pin pqfp 256-pin fineline bga 256-pin bga -10 back to top table 18. max 3000a industrial temperature support device package (1) speed grade epm3032a 44-pin plcc 44-pin tqfp -10 epm3064a 44-pin plcc 44-pin tqfp 100-pin tqfp -10 epm3128a 100-pin tqfp 144-pin tqfp 256-pin fineline bga -10 epm3256a 144-pin tqfp 208-pin pqfp 256-pin fineline bga -10 epm3512a 208-pin pqfp 256-pin fineline bga -10 back to top table 19. max 7000 industrial temperature support device package (1) speed grade file:///p|/alte.htm (10 of 14) [1/18/2005 11:17:26 am]
industrial temperature device support epm7032 44-pin plcc 44-pin pqfp -12 44-pin plcc 44-pin pqfp 44-pin tqfp -15 epm7064 44-pin plcc, 68-pin plcc 84-pin plcc 100-pin pqfp -15 epm7096 68-pin plcc 84-pin plcc 100-pin pqfp -15 epm7128e 100-pin pqfp -15 84-pin plcc 100-pin pqfp -20 epm7160e 100-pin pqfp 160-pin pqfp -15 84-pin plcc 160-pin pqfp -20 epm7192e 160-pin bga -20 epm7256e 192-pin pga 208-pin rqfp -20 back to top table 20. max 7000s industrial temperature support device package (1) speed grade epm7032s 44-pin plcc 44-pin tqfp -7 epm7064s 44-pin plcc 44-pin tqfp 84-pin plcc 100-pin tqfp -7 file:///p|/alte.htm (11 of 14) [1/18/2005 11:17:26 am]
industrial temperature device support epm7128s 84-pin plcc 100-pin pqfp 100-pin tqfp 160-pin pqfp -10 epm7160s 84-pin plcc 100-pin tqfp 160-pin pqfp -10 epm7192s 160-pin pqfp -10 epm7256s 208-pin rqfp -10 back to top table 21. max 9000 industrial temperature support device package (1) speed grade epm9320 84-pin plcc 208-pin rqfp -20 epm9320a 84-pin plcc 208-pin rqfp -10 epm9560 208-pin rqfp 240-pin rqfp 304-pin rqfp -20 epm9560a 208-pin rqfp 240-pin rqfp -10 back to top table 22. classic industrial temperature support device package (1) speed grade ep610 24-pin cerdip 24-pin pdip -30 ep610i 28-pin plcc -12 file:///p|/alte.htm (12 of 14) [1/18/2005 11:17:26 am]
industrial temperature device support ep910 40-pin cerdip 40-pin pdip 44-pin plcc - 35 ep910i 40-pin cerdip -15 44-pin plcc -12 ep1810 68-pin plcc -25, -45 back to top table 23. configuration device industrial temperature support device package (1) epc1064 (65 kbit) 8-pin pdip 20-pin plcc epc1213 (200 kbit) 8-pin pdip 20-pin plcc epc1441 (440 kbit) 8-pin pdip 20-pin plcc 32-pin tqfp epcs1 (1 mbit) 8-pin soic epc1 (1 mbit) 8-pin pdip 20-pin plcc epc2 (2 mbit) 20-pin plcc 32-pin tqfp epcs4 (4 mbit) 8-pin soic epc4 (4 mbit) 100-pin pqfp epc8 (8 mbit) 100-pin pqfp epc16 (16 mbit) 100-pin pqfp notes: 1. bga: ball-grid array pdip: plastic dual in-line package file:///p|/alte.htm (13 of 14) [1/18/2005 11:17:26 am]
industrial temperature device support plcc: plastic j-lead chip carrier pqfp: plastic quad flat pack rqfp: power quad flat pack soic: small-outline integrated circuit tqfp: thin quad flat pack back to top related links l altera ? device literature l max ii devices l stratix devices l cyclone devices l apex ii devices l mercury devices l apex 20k devices l flex 10k devices l flex 6000 devices l max 7000, max 7000a & max 7000b devices l max 9000 devices l classic devices l configuration devices rate this page please give us feedback sign up for e-mail updates home | products | support | system solutions | technology center | education & events | corporate | buy on-line devices | design software | intellectual property | design services | dev. kits/cables | literature contact us | new user | site map | privacy | legal notice copyright ? 1995-2005 altera corporation, 101 innovation drive, san jose, california 95134, usa file:///p|/alte.htm (14 of 14) [1/18/2005 11:17:26 am]

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